OpenOCD Config for VisionFive 2

VisionFive 2 （English Forum)
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#1

By referencing various posts in the forums about connecting via JTAG to the VF and VF2 I’ve been able to successfully connect to the VF2 with OpenOCD. Wanted to share my configuration:

The e24 target is commented out due to being unable to connect. Given I don’t know what that core is used for, I don’t need it.

reset_config trst_only

transport select jtag

adapter speed 4000

jtag newtap e24 cpu -irlen 5 -expected-id 0x07110cfd
jtag newtap u74 cpu -irlen 5 -expected-id 0x07110cfd

#target create e24.cpu0 riscv -chain-position e24.cpu -coreid 0
target create u74.cpu0 riscv -chain-position u74.cpu -coreid 0 -rtos hwthread
target create u74.cpu1 riscv -chain-position u74.cpu -coreid 1
target create u74.cpu2 riscv -chain-position u74.cpu -coreid 2
target create u74.cpu3 riscv -chain-position u74.cpu -coreid 3
target create u74.cpu4 riscv -chain-position u74.cpu -coreid 4
target smp u74.cpu0 u74.cpu1 u74.cpu2 u74.cpu3 u74.cpu4

init

See the image below for where the JTAG pins are on the GPIO.

image
image1035×694 61.3 KB

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#2

From the JH7110 datasheet (page 14 or Section 2.1) there are 6 RISC-V cores in the CPU Subsystem.
U74 MC (5.12 CoreMark/MHz):
4 × RV64IMAFDCBSUX U74 Application Cores (5.75 CoreMark/MHz)
1 x RV64IMACU S7 Core (estimated 2.6 CoreMark/MHz)
U74 and S7 cores are fully-coherent
E24:
1x RV32IMFC E24 Core (3.31 CoreMark/MHz)

There is some source code with the potential to communicate with the E24 core from Linux using shared memory, a mailbox and I think interrupts.

Looking at the CoreMark score it is not like the E24 would not be useful, could even be used as a asynchronous maths co-processor since it supports single-precision floating-point. It could generate an interrupt when it has results and wants a new block of data to process.

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