An S76 is technically a S7-series RISC-V core, just like a U74 is technically a U7-series core. And I see S76 mentioned in more and more places with regard to the U74-mc.
Travelling all the way back in time to 2018-08-22, there was no option to license a S7 Core from SiFive, but there was a S7 Series S76 Core.
So I do still think that it is really an S76 core, without any form of floating point support (FD), without support for Bit Manipulation specifically not Zba and not Zbb (B), with a smaller cache L1 I-Cache, with a smaller Data TIM instead of a Data cache and without a Instruction TIM (basically remove everything so that much less space on the silicon die, and less power, is required). And unlike the U74 (Machine,Supervisor,User mode) it does not have a Supervisory mode just like a S76 Core.
EDIT:
I found CSR MISA information about the 5 hart’s here:
Info : hart 0: XLEN=64, misa=0x8000000000901107
Info : hart 1: XLEN=64, misa=0x800000000094112f
Info : hart 2: XLEN=64, misa=0x800000000094112f
Info : hart 3: XLEN=64, misa=0x800000000094112f
Info : hart 4: XLEN=64, misa=0x800000000094112f
Converting to binary and consulting the “Encoding of Extensions field in misa” table in the riscv-privileged-20211203.pdf gives the following
6666555555555544444444443333333333222222222211111111110000000000
3210987654321098765432109876543210987654321098765432109876543210
--------------------------------------------------------------------
S76 1000000000000000000000000000000000000000100100000001000100000111
U74 1000000000000000000000000000000000000000100101000001000100101111
U74 1000000000000000000000000000000000000000100101000001000100101111
U74 1000000000000000000000000000000000000000100101000001000100101111
U74 1000000000000000000000000000000000000000100101000001000100101111
bit 63=1 ==> MXL (Machine XLEN) the native base integer ISA is 64-bit
bit 23=1 ==> X: Non-standard extensions present
bit 20=1 ==> U: User mode implemented
bit 18=1 ==> S: Supervisor mode implemented
bit 12=1 ==> M: Integer Multiply/Divide extension
bit 08=1 ==> I: RV32I/64I/128I base ISA
bit 05=1 ==> F: Single-precision floating-point extension
bit 03=1 ==> D: Double-precision floating-point extension
bit 02=1 ==> C: Compressed extension
bit 01=1 ==> B: Tentatively reserved for Bit-Manipulation extension
bit 00=1 ==> A: Atomic extension
From the above the letters are (but in a illegal format):
1x S76 is a RV64IABCMUX
4x U74 is a RV64IABCDFMSUX
So more precisely it is:
1x S76 rv64imacux_Zba_Zbb
4x U74 rv64imafdcsux_Zba_Zbb
And even more precisely:
F implies Zicsr, but it may be present even if F is not (e.g. The Core IP had optional F support)
G implies IMAFDZicsr_Zifencei
1x S76 rv64imacuxZba_Zbb_Zicsr
4x U74 rv64imafdcsuxZba_Zbb_Zifencei_Zicsr
EDIT: I now suspect this, but i could be wrong:
1x S76 rv64imacuxZicsr_Zifencei_Zba_Zbb_Sscofpmf
4× U74 rv64imafdcsuxZicsr_Zifencei_Zba_Zbb_Sscofpmf
and at a guess the E24 co-processor is probably:
1x E24 rv32imfcuxZicsr
I guess it is time to start trying to figure out how to get more details on the E24.