VisionFive2 hypervisor extension

VisionFive 2 （English Forum)
1

Does the VisionFive2 have support for the H (Hypervisor) extension?

And if it does support the H extension, any tricks to get KVM to work on kernel 5.15?

2

No, it does not. The U74 is RV64GFC due to the data sheet. This means you cannot run a hypervisor, but nevertheless containers.

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3

It’s JH7110, not JH7100, but sure it’s the same core. The G implies F, but it has B, so maybe you meant RV64GCB?

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4

not all B are in this core though, just zba and zbb

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5

Hmm, the specs have CSR “misa” which spells all the extensions. But unfortunately, this is on machine level. I wonder if this can be accessed some way.

6

It is a privileged operation, that can only be read in machine mode. Looking at the boot up sequence:

ZSBL ROM (Machine mode)
SPL+U-Boot (Machine mode)
U-Boot+OpenSBI(Machine mode → Supervisor mode)
Linux kernel (Supervisor mode)
Linux services/applications (User mode)

There exists a function in Das U-Boot to read any RISC-V CSR:

So I wonder would the simplest way be to add a new U-Boot riscv command (possibly just called “csr”) that can read any CSR, including the MISA (0x301), and just prints hex values or expands it with the information contained in the “Machine-Level CSRs” section of the RISC-V ISA Privileged Specification (riscv-privileged.pdf) to display a more human readable format.

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7

Hmm, the specs have CSR “misa” which spells all the extensions.

That has long been essentially deprecated as it can’t cover the full gamut of extensions. The device tree is where you are supposed to specify this.

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8

This conversation is a little off in the weeds, but doesn’t /proc/cpuinfo give you the full alphabet soup of extensions?

To the original question, this core definitely predates ‘H’. I don’t think SiFive does H until 650.

The gap between specifications being ratified and being able to get them in a real chip on a real board is pretty long. JH-7110 is the first really high-volume, low-cost version of the U7 family which was announced in 2018 or so. Also, Hypervisor was a particularly contentious extension; it wasn’t frozen until December of '21.

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9

No, /proc/cpuinfo doesn’t show zba zbb.

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10

What are all the RISC-V extensions, and versions, in the JH7110 SoC ?
U74-MC:
4x U74:
RV64IMAFDC_Zicsr_Zifencei_Zba_Zbb_Sscofpmf
or
rv64imafdczbb0p93_zba0p93_zicsr_zifencei_sscofpmf

1xS7:
RV64IMAC_Zicsr_Zifencei_Zba_Zbb_Sscofpmf
or
rv64imaczbb0p93_zba0p93_zicsr_zifencei_sscofpmf

1xE24:
RV32IMFC_???

11

Ah, yes, that’s familiar now. That seems to be regarded as an unimplemented feature the official kernel is sure to do Someday. It’s come and gone a few times in various branches, it seems.

Relevant (to this, not the OP) discussion:

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12

But this would mean, the device tree has glitches in jh7110.dtsi:

cpu0: cpu@0 {
     compatible = "sifive,u74-mc", "riscv";
     riscv,isa = "rv64imac";   // << fd? extensions?
};

cpu1: cpu@1 {
     compatible = "sifive,u74-mc", "riscv";
     riscv,isa = "rv64imafdc"; // << extensions?
};
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13

U74-MC consists of:

cpu0 a S7  RV64IMAC
cpu1 a U74 RV64IMAFDC
cpu2 a U74 RV64IMAFDC
cpu3 a U74 RV64IMAFDC
cpu4 a U74 RV64IMAFDC

EDIT: The JH7110 has (S7->S76):

cpu0 a S76 RV64IMAFDC ???!!! instead of RV64IMAC ???!?!?!?
cpu1 a U74 RV64IMAFDC
cpu2 a U74 RV64IMAFDC
cpu3 a U74 RV64IMAFDC
cpu4 a U74 RV64IMAFDC

And accessed from the U74MC4+U76 across frontport0 axi4 @ 128bit 750MHz bus is a E24 RV32IMFC.

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