VisionFive2 hypervisor extension

To be clear, are you refering to GitHub - starfive-tech/linux at JH7110_VisionFive2_upstream ?

S7_0 cpu@0 rv64imac_zba_zbb
U74_1 cpu@1 rv64imafdc_zba_zbb
U74_2 cpu@2 rv64imafdc_zba_zbb
U74_3 cpu@3 rv64imafdc_zba_zbb
U74_4 cpu@4 rv64imafdc_zba_zbb

E24 is no longer listed in JH7110_VisionFive2_upstream. It was removed from the dts files, but then again it is a difficult CPU to make good use of, it is 32-bit, asynchronous and without a MMU.


Humm, bummer. Actually it’s one of the things that attracted me to the board.

I want to run a real-time machine control application on the E24 that runs independently of the OS etc, My goal is to run three stepper motors and a laser.


… See the Pi3 in there (it has a 3.5’ screen)… Eventually the VF2 replaces that.

I was going to build another custom ESP32 controller for this (FluidNC) but thought it could be neat to drive the controller directly without needing the ESP32.

The E24 is nearly ideal for this, and no MMU is no problem, no serious maths to do. It was labelled as a ‘realtime processor’ in some of the JH7110 literature.

Hopefully it can still be used (or added to the dts as needed).

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AFAIK, only software emulated is there because hw lacks it. You might be interested in getting in touch: GitHub - dramforever/opensbi-h: WIP: A fork of OpenSBI, with software-emulated hypervisor extension support

3 Likes has all you need to know. I just want to stress:

  1. No H extension on either S7 or U7
  2. Apart from lacking floating point in S7, the major difference is that S7 only has 2 modes, M/U. U7 has all 3 modes, M/S/U. Thus, S7 is not well suited for general Linux use. I’m think of using it for profiling other U7 cores through IPI, making it a little bit useful.
  3. For E24, it’s not even mentioned in dts. I had this post earlier about JH7100 (JH7100: Make use of E24?), and recently I asked starfive again about E24 on JH7110. In short, they are not ready to open source the Linux driver code that could load a ELF binary to E24, even though they have testing instructions: soft_3rdpart/e24_test.docx at JH7110_VisionFive2_devel · starfive-tech/soft_3rdpart · GitHub (In Chinese)
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After scanning JTAG chain in JH7110, I found 2 taps, one is u74-mc, another maybe e24, but connection to that would fail, maybe e24 needs to be enabled by register or something.

The problem might be that the E24 has no Boot Vector, the boot vector for the E24 is defined by the U74MC.

I don’t think so… JTAG debug has higher priority than program.

Reading page 134 of “SiFive E24 Core Complex Manual 21G1.01.00” (not sure if it is the right revision of document for the E24 in the JH7110), another possibility might be that the debugger might need to send a halt so that the E24 will wait running in a loop (entry_loop) for debugger instructions.

Table 98 “Debug Module Memory Map from the Perspective of the Core” from that page:

TL Address Name Attr. Description
0x800‑0xFFF ROM RO Debug interrupt or EBREAK enters at 0x800, saves s0,writes hartid to HALTED, then busy-waits for FLAGS[hartid] > 0. If FLAGS[hartid].go, write 0 to GOING, then jump to WHERETO. Else write hartid to RESUMING, then execute dret to return to user program. ROM Source Code: