Besides the dual gig ethernet on 1.3B, are there any known/significant hardware differences between both versions of VF2? I’d guess probably not, but figured I’d ask to be sure!
I compared the two schematics, RV002_V1.3B_20230208.PDF to the earlier SCH_RV002_V1.2A_20221216.pdf, and the only change in the schematic I noticed was more precise labelling of some part numbers e.g.
1.2A: Y6003 32.768KHz CRY-3215
1.3B: Y6003 SF32K32768D31T-12.5B
Other than you mentioned, the NIC’s, speed reading through the two schematics I did not notice anything else, but I might have missed something:
PHY0 YT8531C U6 10/100/1000Mbit/sec
PHY1 YT8512C U39 10/100Mbit/sec
PHY0 YT8531C U6 10/100/1000Mbit/sec
PHY1 YT8531C U7 10/100/1000Mbit/sec
VF2 1.2A eth1 100M network port with 1.3B 1000M network port,Other interfaces remaining consistent.
I also read that there was an upgrade to 4 USB 3 ports.
I assumed it was a hardware upgrade (or at least some hardware change), but looking at the comments on Kickstarter, they claim all boards have it. So it was a firmware or software upgrade?
“All versions including the previously released super-early-bird have 4x USB 3.0, compatible with USB 2.0.All versions including the previously released super-early-bird have 4x USB 3.0, compatible with USB 2.0.”
I tested all ports on my “A” board, and it reported in
lsusb that all are USB 3.0.
One thing to keep in mind is that the “VIA VL805 PCIe to quad port USB 3.0” is a USB hub chip. So the total throughput of all ports in use simultaneously would be limited in theory to the maximum data throughput rate, less any overheads, of a single PCIe 2.0 1x lane (500MB/sec) on the JH7110. USB 3.0 is full duplex, so that would nearly be reading 500MB/sec input while simultaneously writing 500MB/sec output less any overheads. With near optimal real world hardware and drivers the upper limit is usually closer to 400 MB/sec.
I just looked at the schematic again and there is one other change and that is the the USB C port which was used for power only in the 1.2A board now also provides a USB 2.0 High Speed port (Which does not support OTG) via the JH7110 SoC (pin A16 : USB Data minus and pin A15 : USB Data Plus). Making use of it may be difficult, but it is there.
May be if you provided power via 5V GPIO pin instead, this port will be available.
I was thinking that there must be some kind of USB-C splitter cable for power and data. Possibly a USB-C to 2 USB-C splitter might work.
USB “splitters” are not supposed to exist, according to the spec, but of course they do. Getting power from both barrel and USB sounds like a hazard waiting to happen, esp. if the port is using USB power deliver and cruising along at 48 volts or whatever the latest PD spec allows. (12 is common…) Either way, connecting power to power via a splitter cable is bad news, even without power delivery.
Actually, the provided power supply is 12V, right?
I’m guessing the most likely case is to accept power and communication while attached to a computer, all from a single cable.
You are only interested in USB 2.0 HS and that is a separate set of wires (than USB 3.0) so 5V, D+, D- and a common ground. So I guess a USB-C splitter in this case would only work if the power supply was 5V @ 3A (15 watt).
That is just it, the port does not support OTG so it would be one power source that would be supplying the USB 2.0 HS (or slower) endpoint device and the VF2 board. Hence why a splitter would only work if the power source supported 5 volts maximum.
Or you could also use that USB 2.0 HS port if you were powering the VF2 using a PoE+ HAT or as @cwt said using 5V GPIO pin(s).
The SoC has a USB2 controller built in. I imagine the original plan was to expose it in 2 ports, and use the VIA chip for the other two. Then they switched to not using the SoC’s USB at all, and exposing all 4 USB3 ports from the VIA.
The questions remains whether the SoC’s USB2 can be presented in the GPIOs instead, so that we can make use of them regardless.
No is the answer.
From the JH7110 datasheet (2.6.2. USB):
▪ Single USB2.0 Port ▪ Single USB3.0 Port (By reusing 1 of the PCIe2.0 lanes)
And if you look at “Table 4.2. Full Multiplexing”, USB (D+ and D-) is not an available function that can be multiplexed to the GPIO pins.
Looking at the JH7110 datasheet (Figure 3-1 Pin Map), USB is physically tied to the following pins which can not be internally multiplexed to other pins:
Also note that the same lines are going to the M.2 NVMe socket on pins 20 and 22 (iirc, the NVMe m.2 spec lists these pins as N/A.)
I suspect these are changes made to better support bare-metal and embedded JH7xxx developers.
They/we can use a simple usb splitter or NVMe expander to get access to these lines. Really handy for some, StarFive deserve some love for doing this.
It should be possible to have a cable with the USB PD power passing through on the power lines, and a 5v buck plus the data lines tapped out to drive the USB2 hub/connector/whatever. Isolation on the data lines would be a bonus.