From the JH7110 datasheet (page 14 or Section 2.1) there are 6 RISC-V cores in the CPU Subsystem.
U74-MC (5.12 CoreMark/MHz):
4 × RV64IMAFDCSUXZicsr_Zifencei_Zba_Zbb_Sscofpmf U74 Application Cores (5.75 CoreMark/MHz)
1 x RV64IMACU S7 Core (estimated 2.6 CoreMark/MHz)
U74 and S7 cores are fully-coherent
1 x RV64IMAFDCSUXZicsr_Zifencei_Zba_Zbb_Sscofpmf S76 Core (5.67 CoreMark/MHz)
ref: JH7110 Technical Reference Manual which conflicts with the information in the JH7110 datasheet!
4 × U74 rv64imafdcsuxZicsr_Zifencei_Zba_Zbb_Sscofpmf
1 x S76 rv64imacuxZicsr_Zifencei_Zba_Zbb_Sscofpmf
U74 and S76 cores are fully-coherent
E24:
1x RV32IMFC E24 Core (3.31 CoreMark/MHz)
There is some source code with the potential to communicate with the E24 core from Linux using shared memory, a mailbox and I think interrupts.
Looking at the CoreMark score, it is not like the E24 would not be useful, could even be used as a asynchronous maths co-processor since it supports single-precision floating-point. It could generate an interrupt when it has results and wants a new block of data to process.
EDIT: updated S7 to S76 ?!?!?!?
EDIT2: updated U74 and S76. I still suspect it is a S76, but with some default features not included.