I need DRAM training and calibration code or any tool used for VisionFive2 board.
I have VisionFive2 board and I’m currently going through the u-boot and Linux porting to that board.
I need to understand the DRAM training and DRAM initialization code flow in u-boot source code.
It is highly appreciated if anyone could help me to achieve my present milestone.
The best place to look for the most current code is in starfive-tech/u-boot/drivers/ram/starfive/
And then the best place to look for some comments that might help you decipher the meaning with help from the link posted by @tunagenes will probably be by searching (rgrep string *) a local copy the slightly older code in starfive-tech/JH7100_ddrinit/ for an exact or partial match to the most recent code.
Unfortunately most current DDR initialisation code is covered by NDA’s (Non Disclosure Agreement’s), so detailed information is usually hard to find.
P.S. I know that the JH7100 is not the JH7110 used in the VF2 board, but most of the DDR code will be close enough, just a lot more compact, with almost no comments, in the U-Boot code.
Thanks for your valuable response as it is very useful.
I have already gone through the below mentioned file:
**boot/drivers/ram/starfive/ ddrcsr_boot.c, ddrphy_start.c, ddrphy_train.c, ddrphy_utils.c, starfive_ddr.c starfive_ddr.h
The function in these files get called after starfive_ddr_probe() function gets called from device tree.
I want to know how this starfive_ddr_probe() function gets called in SPL/u-boot source code as well as DDR PHY Regs description and DDR controller TRM of Startfive JH7110 SoC.
It will be very helpful if could let me know something regarding this.
@mzs - I don’t doubt that is true, but I would like to find out more about it. Specific questions:
Who would the NDA be between - VisionFive and the DRAM manufacturer, or someone else?
What is the motivation for keeping this ‘secret’?
How do you know this?
Thank you for any insight you can provide. It seems a shame to have binary blobs showing up so early on a RISC-V based system.
I tried a Google search on “DRAM training and calibration nda” but didn’t find any useful results.
The information you seek would all be contained in “JEDEC Standard JESD209-4D”
The security to prevent companies who have not paid to have JEDEC documents is simple, JEDEC will physically ship your company a hard copy of their documentation in a number of ring binders and then email updates for a yearly subscription fee. And I’m sure that everything is digitally water marked these days. So you are pretty much guaranteed not to find much of their documentation online.
As for the motivation to keep things secret. In my opinion it is to keep small players on the outside (unless they can pay enough yearly to join). The members of JEDEC create the standards in committees formed by the member companies, each would be pushing to move the standard towards their preferred solution. I also think of it as an anti-competitive agreement between members. It is also a cheap way to keep time wasters away (companies that will not be shipping 10k to 100M product units a year). They have been about for nearly a century, formed in 1924 by the Radio Manufacturers Association. Then in 1944 became JETEC - Joint Electron Tube Engineering Council. And finally in 1958 they renamed to JEDEC - Joint Electron Device Engineering Council. So I’m sure part of the reason for not giving away their documentation for free is historic, creating documentation costs money, physically shipping documentation costs money. Historically there would have been a lot of travel, which would require accommodation, and physical meetings involved in creating standards, money for that needed to come from somewhere. Selling NDA documentation is also an additional revenue stream, that would reduce the membership fees for the very largest companies who can afford to assign “free” resources into committees to create and update the documentation of the standards.
Thanks for the info and your opinions-insight @mzs ! I don’t disagree with anything you said, but I think there’s gotta be a better way to do this so that how the basic technology works is less hidden. But I’ll stop whining-preaching and get back to the real world now. I appreciate you taking the time to answer.
Thanks for your response.
Presently, I’m going through the Starfive2 board’s DDR training and initialization code but to understand it properly I need JH7110 SoC’s DDR controller TRM and DRAM device datasheet.
So, please let me know if there is any such document which provides the details of the registers and programing flow for DRAM initialization and training .