DRAM Calibration and Training In u-boot

VisionFive 2 （English Forum)
1

Hi @tunagenes and Others,

I have gone through the both repos but not able to map regarding calibration and r/w training.

https://github.com/starfive-tech/u-boot/tree/JH7110_VisionFive2_devel/drivers/ram/starfive
and
https://github.com/starfive-tech/JH7100_ddrinit/blob/starfive/ddrc_cfg/lpddr4_1600_cl28_bl16/orbit_boot_1600.c

In the following files, I’m not able to find out where the DRAM calibration and Read/write training take place in code.
ddrcsr_boot.c, ddrphy_start.c, ddrphy_train.c, ddrphy_utils.c, starfive_ddr.c starfive_ddr.h

I’m also not able to understand what the following while loop is doing in “ddrcsr_boot.c” file.
Is it doing training ?

while ((val & 0x2) != 0x0) {
val = in_le32(phyreg + 1);
if ((val & 0x20) == 0x20) {
switch (val & 0x0000001f) {
case 0: //ddrc_clock=12M
DDR_REG_SET(BUS, DDR_BUS_OSC_DIV2);
break;
case 1: //ddrc_clock=200M
DDR_REG_SET(BUS, DDR_BUS_PLL1_DIV8);
break;
case 2: //ddrc_clock=800M
DDR_REG_SET(BUS, DDR_BUS_PLL1_DIV2);
break;
default:
break;
};

                    out_le32((phyreg + 2), 0x1);
                    do {
                            udelay(2);
                            val = in_le32(phyreg + 2);
                    } while ((val & 0x00000001) != 0x00000000);
            }
            udelay(1);
            val = in_le32(csrreg + REGOFFSET(0x518));
    };

Thanks,
Novice

1 Like
2

And now for something completely different

2 Likes
3

Hi @SunWukong,

I have got some helps from that which you mentioned but this post regarding DRAM training code related queries.
I want know that any calibration and training is happening here or just pre-trained values have been used.

Thanks,
Novice