Thanks,
It is good to see some public info about the Fang Jinhong 8100 (Even though it will probably take a year, or two, until it is ready to enter mass production and be available on a VisionFive 3 board):
JH8100:
self developed Tianshu RISC-V CPU
large cores (high performance) and small cores (low power)
self developed NOC (Network-on-Chip) bus Starlink 1.0
Interesting. It was surprisingly hard to find hard data about this. The Russian nested dolls goes like this: VisionFive 3 sporting a Fang Jinhong 8100 SoC, using a Tianshu RISC-V CPU, powered by the Dubhe core.
What I gleaned was 8.9/GHz SPECint2006, 8-wide fetch, 5-wide dispatch, 10-wide issue, 10-wide commit. Supports B, V, and H (in addition to the usual stuff). CPU width is defined by the narrowest part so this is a 5-wide core, originally designed for 3.5 GHz@TSMC 7nm, but apparently launching at 2.0 GHz@12 nm (still TSMC?).
This would be the fastest widely available consumer-grade RISC-V CPU today, but I suspect it won’t hold that record for long if it isn’t launching until two years from now (~ 5 years after announcement).
The silicon should have been taped out at the end of 2022, so I would allow 6 months if absolutely everything worked perfectly on the very first revision of the silicon, but in reality it is usually two or three spins until a fully working chip is produced that is where my one to two year comes from. Making new silicon, with new self developed features, is not a fast process. One of the reasons for buying off the shelf IP for chips is that it has usually been produced by many fabs and has been fully debugged. It will also probably need to be produced at SMIC instead of TSMC, due to the current United States Department of Commerce sanctions.
B was only “Tentatively reserved for Bit operations”, and never actually ratified, and has changed status back to reserved for future use. The main Bit Manipulation ISA extensions that were ratified in 2021-11 are: Zba, Zbb, Zbc, Zbs.
