VisionFive 2 Ecosystem Bi-weekly Updates (5.01-5.15)

StarFive News

  1. Python Library Status Updates for VisionFive Series SBC

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  1. Unlocking New Possibilities: StarFive VisionFive 2 SBC Now Supports TianoCore EDK II (UEFI)
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Community Collaboration

  1. Canonical enables Ubuntu on StarFive’s VisionFive 2 RISC-V single board computer
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  1. OpenSUSE released an updated official image for StarFive VisionFive 2 SBC on May 12th
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  1. RISC-V With Linux 6.4 Adds Hibernation / Suspend-To-Disk Support!
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Social Media Updates

  1. Twitter user 北雁山前 Estela ad Astra shared a cool page served from VisionFive 2 SBC

    Click this link to see the page.

  2. Debian Installer Bookworm RC 2 release added support to VisionFive SBC

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  1. Haiku OS forum user X512 got Haiku desktop with USB working on VisionFive 2. Booted from NVMe. Four CPU cores are working.

    Click this link to see the amazing progress.
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  1. RVspace user Tan_Chun_Hau shared his experience in using VisionFive2 RISCV SBC as EtherCAT Master

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  1. Demo 13 | Tutorial on Using Line Patrol Sensors on VisionFive 2

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  1. Demo 12 | Tutorial on using fire alarm devices on VisionFive 2
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  1. StarFive and China Telecom Complet e the First RISC-V Cloud Native Lightweight Virtual Machine Verification
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  1. This manufacturer leads the development of high-end RISC-V chip industry
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  1. Run Altlinux on VisionFive 2

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All the social meida updates are collected from the Internet, if you have any doubt, please contact the source of the information for clearance.

10 Likes

Thanks,
It is good to see some public info about the Fang Jinhong 8100 (Even though it will probably take a year, or two, until it is ready to enter mass production and be available on a VisionFive 3 board):

JH8100:

  • self developed Tianshu RISC-V CPU
    • large cores (high performance) and small cores (low power)
  • self developed NOC (Network-on-Chip) bus Starlink 1.0
  • advanced 12nm process
  • low power consumption
  • powerful multimedia capabilities
    • 4K@60 fps
    • decode: H264/H265/VP9/AV1
  • USB 3.0/2.0
  • x4 USB 3.2 Gen2 TypeC
  • PCIe3.0 x8
  • Artificial Intelligence
    • 2 TOPS AI computing power
    • supports mainstream architectures like TensorFlow
11 Likes

Interesting. It was surprisingly hard to find hard data about this. The Russian nested dolls goes like this: VisionFive 3 sporting a Fang Jinhong 8100 SoC, using a Tianshu RISC-V CPU, powered by the Dubhe core.

The latter is the interesting bit and this page appears to have info for Chinese reading audiences: https://mp.weixin.qq.com/s/yFZQW-7jEH4mN0Xolz8XEg

What I gleaned was 8.9/GHz SPECint2006, 8-wide fetch, 5-wide dispatch, 10-wide issue, 10-wide commit. Supports B, V, and H (in addition to the usual stuff). CPU width is defined by the narrowest part so this is a 5-wide core, originally designed for 3.5 GHz@TSMC 7nm, but apparently launching at 2.0 GHz@12 nm (still TSMC?).

This would be the fastest widely available consumer-grade RISC-V CPU today, but I suspect it won’t hold that record for long if it isn’t launching until two years from now (~ 5 years after announcement).

3 Likes

The silicon should have been taped out at the end of 2022, so I would allow 6 months if absolutely everything worked perfectly on the very first revision of the silicon, but in reality it is usually two or three spins until a fully working chip is produced that is where my one to two year comes from. Making new silicon, with new self developed features, is not a fast process. One of the reasons for buying off the shelf IP for chips is that it has usually been produced by many fabs and has been fully debugged. It will also probably need to be produced at SMIC instead of TSMC, due to the current United States Department of Commerce sanctions.

B was only “Tentatively reserved for Bit operations”, and never actually ratified, and has changed status back to reserved for future use. The main Bit Manipulation ISA extensions that were ratified in 2021-11 are: Zba, Zbb, Zbc, Zbs.

4 Likes

5 USB ports, 1 PCIe port with 8 channels

1 Like