My starting point would be the datasheet (or the Product Brief) for the JH7110 SoC (ref: https://doc-en.rvspace.org/ ). Since that would be the maximum that would be possible in theory.
The SoC has support for two PCIe2.0 1x lanes
And one of those PCIe 2.0 1x lanes is being used to add a two port USB 3.0 hub on the VisionFive 2 board.
So that would imply that the M.2 connector has a dedicated PCIe 2.0 1x lane.
And if you lookup what x1 lane is on PCIe 2.x, in terms of raw signalling, that would be 5 GT/sec.
But since PCIe 2.x uses an 8b/10b signal encoding scheme that would be a maximum theoretical data throughput rate (if there were no overheads in the protocol used) of 4 Gbit/second (500MB/sec or nearly 477 MiB/sec).
That would be, my assumption for, the absolute theoretical maximum anyhow.