What is the status of PCIe on this board?

The description says it has M.2 connector with m-key.

How many PCIe lanes are available at the M.2 connector?

What is the speed of the PCIe implementation?

Can you please provide more details about PCIe support?

Thanks in advance!

My starting point would be the datasheet (or the Product Brief) for the JH7110 SoC (ref: https://doc-en.rvspace.org/ ). Since that would be the maximum that would be possible in theory.

The SoC has support for two PCIe2.0 1x lanes
And one of those PCIe 2.0 1x lanes is being used to add a two port USB 3.0 hub on the VisionFive 2 board.
So that would imply that the M.2 connector has a dedicated PCIe 2.0 1x lane.
And if you lookup what x1 lane is on PCIe 2.x, in terms of raw signalling, that would be 5 GT/sec.
But since PCIe 2.x uses an 8b/10b signal encoding scheme that would be a maximum theoretical data throughput rate (if there were no overheads in the protocol used) of 4 Gbit/second (500MB/sec or nearly 477 MiB/sec).

That would be, my assumption for, the absolute theoretical maximum anyhow.


Not to detract from VisionFive 2, but if you’re looking for PCIe in a “normal” form factor, at least look at this board’s sibling, the Pine64. It’s made less noise, but I think it should be on the market about the same time as VF2.

I don’t know if you can figure out lane configuration just from te picture or not, but there may be a hint here, since you know the primary SoC and can tell there’s not a huge amount of supporting circuitry.



The exact same SoC is on both boards (JH7110).

The big difference, from my point of view, is that pine64 has not finalised (publicly) between a KSZ9031RNXCA and YT8521 GMAC phys. The prototype board schematic showed a FPGA Mezzanine Connector, so that multiple options could be tested.
They will offer single or dual 10/100/1000Mbps ethernet board.
They will have one USB3.0 dedicated Host port (which I am guessing will use the same PCIe 2.0 1x lane as the VisionFive 2 board, since I do not see any other way of providing a USB 3.0 interface).
And that would imply that the PCIe slot is version 2.0 and has a 1x lane.

There is one tiny advantage, that I can see for the Star64 board, and that is that the board has a 33% physically larger surface area (133 x 80 mm) compared to the VisionFive 2 board (100 x 72 mm - Pico-ITX form factor). That means that it should have more surface area for potentially greater air flow to dissipate heat faster, and under the same operating conditions it should run slightly cooler.

The Arrhenius Equation (summary: the chemical reaction rate doubles every time the temperature increases by 10 degrees Celsius), when flipped and applied in reverse to individual electronic components basically means that every 10°C (18°F) lower the operating temperature of electronic devices should potentially double the expected usable average lifetime. I know it sounds odd, but large ovens are used in the semiconductor industry to force accelerated ageing of parts that would have failed in the “early infant mortality failure” stage of the bathtub curve.

But at the end of the day, it is only an advantage for passive cooling. And once you put anything inside a box that constrains the flow of air that is effectively an oven. So if you are putting the board inside a box (with active cooling) the VisionFive 2 board, which should fit inside any standard Pico-ITX cases, might also have an advantage.

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VF2’s M.2 slot supports pcie2.0 x1lane, Support link rate of 2.5, 5.0 GT/s per lane.
Here is the specifications of JH7110 and Visionfive2 on our wiki, you can take a look.

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