What is a "Thread toolchain"?

On a Sipeed wiki were they describe Lichee Pi 4A board there are some benchmarks comparing this board to few others including VF2. Benchmarks They have two sets of results, one with what they call “public toolchain” and another with what they call “Thread toolchain”, later results being much higher. What is this “Thread toolchain”? Is it some kind of proprietary compiler? It’s hard to understand why it would be so much better in producing fast code.


its “THead” toolchain, not thread… (source is here: GitHub - T-head-Semi/xuantie-gnu-toolchain: GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……)
its a fork of GCC that includes support for 0.7.1 Vector Extension (which is included in the TH1520 CPU).

But… their benchmarks don’t really match reality. A lot of people are not able to reproduce those results… so take with a grain of salt.


Thanks! I just got this board and I have VF2. I’ll look into running this and will post results.

If you have the misfortune of using a T-Head core, I know it’s tempting (and fair game…) to use every opcode available on those parts, but when I looked at the output, they made such heavy use they no longer even really resembled RISC-V opcode streams.

That may or may not matter to you and your sense of RISC-V “purity” vs. performance from a device you purchased doesn’t have to match mine, but I avoid the T-Head chain - and parts - for amongst those reasons. I’m no longer helping RISC-V, building RISC-V apps; I’m building T-Head apps. If you’re a software developer tuning your app or tools, you’re no longer targeting “RISC-V”, but rather “RISC-V Accented Thead ISA”.

There will be people that are fine with that. I just hope they know that’s what’s at the end of the “Just onnnnne more T-head extension” cookie crumb trap is. But if you, for example, just bought 50,000 of these and your goal is to make them go as fast as you can with blinders on to the rest of the world, go nuts. That’s a totally valid thing to do with your time. it’s as valid as tuning your data center code for EPYC and not caring that the resulting binaries don’t run on Xeon.

Just don’t pretend it’s RISC-V unless it runs on another RISC-V CPU. That’s one major point of “open”, after all.

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