In the display subsystem, block diagram, which I am guessing was copied from the JH7100 SoC, it displays the video encoding happening in the JH7110 using a “WAVE521 (Enc)” instead of a “WAVE420L (Enc)”.
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I noticed in passing that the v1.3b schematic, page 22, is for USB Tpye-C Power
@starfive : If you created a github repo to publish your documentation on we could divert these comments and just raise a short issue on github.
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In the System Architecture->Memory Map->U74 Memory Map section I suspect that there is a copy and paste typo:
Start Address | End Address | Size | Attribute | Device |
---|---|---|---|---|
0x00_0110_1000 | 0x00_0110_1FFF | 8KB | RWX A | S7 Hart0 DTIM |
0x00_0170_0000 | 0x00_0170_0FFF | RW A | S7 Hart0 Bus-Error Unit | |
0x00_0170_1000 | 0x00_0170_1FFF | RW A | U7 Hart1 Bus-Error Unit | |
0x00_0170_2000 | 0x00_0170_2FFF | RW A | U7 Hart2 Bus-Error Unit | |
0x00_0170_3000 | 0x00_0170_3FFF | RW A | U7 Hart3 Bus-Error Unit | |
0x00_0170_4000 | 0x00_0170_4FFF | RW A | U7 Hart3 Bus-Error Unit |
I think that the second Hart3 should probably be Hart4.
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