Hey StarFive Team,
Pledged 4GB VisionFive 2 on Kickstarter! I do have a query regarding it. What is the open-source status of the board and what is not open source and proprietary in the board. I understand that GPU would be non open source… but I want to know what else it covered under NDA or non open source. A list of it will be of great help.
Thanks
Hi Tintin,
Actually GPU will be open-sourced in the future by Imagination. However the release time is not predictable so I assume it may take long time. We will upstream our JH7110 (chip in VisionFive 2) to Linux Kernel and open source our SDK, toolchain, datasheet and other related documentation. The part we might not be able to fully open source is our hardware design (part of TRM for example).
Is TRM, Technical Reference Manual ?
So I am guessing because the SoC (System On a Chip) contains blocks of third party IP that required an Non-Disclosure Agreement(NDA) and are accessed via the Advanced eXtensible Interface(AXI) protocol/Network On Chip(NOC) bus, that not all of the register addresses and functions can be publicly shared (until the patents involved eventually expire, worst case in 20 years time) without a NDA signed with the companies that own the IP block. I’m going to randomly guess MIPI(everything related to the mobile phone industry is full of NDA’s), DDR4 IO, PCIe.
A “Non-Disclosure Agreement” means that StarFive can’t talk about what they are not allowed to talk about! So an answer they may be allowed to answer is which block accessed via AXI/NOC in the JH7110 block diagram will have full documentation (since you are not asking for information that they legally can not disclose, because they signed documentation that forbids them from talking about it.):
I suspect that I might be able to remove all the blocks above that correspond to IP owned by SiFive, ones that they have publicly published hardware description language (HDL) files: gpio ; i2c ; jtag ; pwm ; spi ; timer ; uart ; wdt
( ref: https://www.kernel.org/doc/Documentation/devicetree/bindings/sifive/sifive-blocks-ip-versioning.txt and https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices )
I could be wrong, but that would potentially leave:
Without any inside knowledge, but having followed news closely, some of these should be commodity. UART is standard 16550, USB should be xHCI, and such.
These parts are probably incompatible in some ways, but remember that these didn’t just fall from the sky. They’re FU740-based designs and that was used in boards like Unmatched long ago. Hundreds of pages of doc is available on those parts. Between JH7100, Unmatched, and other previous generations, we’ve seen open source OSes work through SiFive/StarFive parts before.
Clearly, SiFive has work to do on publishing the official docs that actually match these parts, but they’ve successfully published enough doc on proceeding parts to allow plenty of OSDev work, so I have faith that there won’t be large blocks of parts that’ll create stalls for work.
Looking at public photos of the VisionFive 2 board, I see what might be a VLI VL805-06 chip near the 4 USB 3.0 ports.
VLI VL805 (4-Port Super Speed USB 3.0 Host controller with a PCIe interface)
https://www.via-labs.com/product_show.php?id=48
Software:
Access to the firmware, documentation, and code I would imagine requires signing an NDA, since there is no public datasheet or even brochure, for this VLI confidential information.
There is some public Linux code for the RPi4 which uploads the VL805 firmware blob via a mailbox request to the Videocore OS in the event of a reset, using non public firmware load logic.
So even though basic xHCI functionality can be got to work (if the VL805 loads its own firmware from say an external EEPROM), some possible features may never be added like the ability to boot an OS from a USB storage device, simply because the NDA’s limit access to the knowledge required. And none of information can be made public, so you could end up with a firmware blob that is installed once and never updated.
I should probably add that is not part of the JH7110 SoC.
Actually I’m wrong the VisionFive 2 board has 2x USB 3.0 ports and 2x USB 2.0 ports so maybe the photo I’ve seen is an older revision and the chip used now is not a VL805 4-Port Super Speed USB 3.0 (It might be a VL806 2-Port Super Speed USB 3.0 or possibly a totally different chip which does not need firmware blobs).
Seeing this: [PATCH v4 0/6] staging: media: wave5: add wave5 codec driver for the JH7100 (which I am guessing would be the same or very similar for the JH7110) would suggest that the H264/H265 Video Decoder/Encoding is probably done using Chips and Media IP, I’m going to guess:
wave511 for hardware decoding
wave521 for hardware encoding
Simply because that is the only hardware currently that firmware blobs are publicly available for from:
But driver code from Collabora to access the blocks over an AMBA3 32bit APB interface appears to be distributed under BSD 3 clause and LGPL2.1 (dual license), which is very nice.
But just to be clear I’m only guessing, I could be and, probably am wrong.
GPL-2.0 licensed code for accessing that hardware via pl080 (?ARM PrimeCell DMA Controller?) can be found at:
Shame it is not dual licensed (would help people who plan on porting *BSD OS’es to the hardware).
I’m wrong from the datasheet for the JH7110, “Figure 5-2 Clock Structure”:
HDMI uses a DC8200 (Verisilicon Inc. IP)
Video Encoder is a WAVE420L (Chips&Media Inc. IP)
Video Decoder is a WAVE511 (Chips&Media Inc. IP)
JPEG Codec is a CODAJ12V (Chips&Media Inc. IP)
Are there any news on the Imagination side of things?