Open-Source Status of VisionFive 2

Hey StarFive Team,

Pledged 4GB VisionFive 2 on Kickstarter! I do have a query regarding it. What is the open-source status of the board and what is not open source and proprietary in the board. I understand that GPU would be non open source… but I want to know what else it covered under NDA or non open source. A list of it will be of great help.

Thanks

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Hi Tintin,

Actually GPU will be open-sourced in the future by Imagination. However the release time is not predictable so I assume it may take long time. We will upstream our JH7110 (chip in VisionFive 2) to Linux Kernel and open source our SDK, toolchain, datasheet and other related documentation. The part we might not be able to fully open source is our hardware design (part of TRM for example).

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Is TRM, Technical Reference Manual ?
So I am guessing because the SoC (System On a Chip) contains blocks of third party IP that required an Non-Disclosure Agreement(NDA) and are accessed via the Advanced eXtensible Interface(AXI) protocol/Network On Chip(NOC) bus, that not all of the register addresses and functions can be publicly shared (until the patents involved eventually expire, worst case in 20 years time) without a NDA signed with the companies that own the IP block. I’m going to randomly guess MIPI(everything related to the mobile phone industry is full of NDA’s), DDR4 IO, PCIe.

A “Non-Disclosure Agreement” means that StarFive can’t talk about what they are not allowed to talk about! So an answer they may be allowed to answer is which block accessed via AXI/NOC in the JH7110 block diagram will have full documentation (since you are not asking for information that they legally can not disclose, because they signed documentation that forbids them from talking about it.):

  • RISC-V 64-bit Quad-core U74 L1$32 KB/32 KB
  • RISC-V 64-bit S7 L1I16KB 8 KB DTIM
  • L2 Cache (2MB)
  • DMAC x2 (?Direct Memory Access Controller?)
  • Mailbox
  • RISC-V 32-bit CPU E24
  • MIPI-CSI (mobile industry processor interface camera serial interface)
  • ISP-RGB (?Image Signal Processors - Red Green Blue?)
  • 12-bit DVP (?Digital Video Port?)
  • GPU (Imagination BXE-4-32 GPU supporting OpenGL ES 3.2, OpenCL 1.2, Vulkan 1.2 GPU)
  • UART x6 (Universal asynchronous receiver-transmitter)
  • SPI x7 (Serial Peripheral Interface)
  • PWM x8 (Pulse Width Modulation)
  • I2C x7 (Inter-Integrated Circuit bus)
  • WDT (Watch Dog Timer)
  • GPIO x64 (General Purpose Input Output)
  • Timer x7
  • eMMC 5.0 x1
  • Audio DSP
  • I2S/PCM-TDM (Inter-IC Sound bus/Pulse Code Modulation-Time Division Multiplexing)
  • I2S/PCM (Inter-Integrated circuit Sound bus/Pulse Code Modulation)
  • PDM x4 (Pulse-density modulation)
  • SPDIF x1 (Sony/Philips Digital Interface)
  • BootROM (32 KB)
  • DDR external memory I/F LPDDR4/DDR4/DDR3/LPDDR3 32-bit, 2800 Mbps
  • QSPI Flash Controller (Cadence Quad SPI IP block)
  • Video Decoder H264/H265 4K @ 60 fps
  • Video Encoder H265 1080p @ 30 fps
  • JPEG Codec
  • HDMI/LCD
  • Display Engine OSD/Overlay
  • MIPI-DSI (mobile industry processor interface display serial interface)
  • PCIe 2.0 1 lane x2* (Peripheral Component Interconnect Express)
  • USB 2.0 Host/Device
  • Ethernet MAC 10/100/1000 Mbps x2
  • CAN 2.0B x2 (Controller Area Network)
  • SDIO 3.0 (Secure Digital Input Output - for MicroSD cards)
  • JTAG (Joint Test Action Group interface - for debugging)
  • Power Managment Unit (PMU) CRG (?Clock Reset Generator?)
  • RTC (Real Time Clock)
  • PLL x3 (Phase Locked Loop)
  • Temp Sensor
  • TRNG
  • OTP (One Time Programmable memory)
  • Secure HW Engine AES/DES/3DES/HASH/PKA
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I suspect that I might be able to remove all the blocks above that correspond to IP owned by SiFive, ones that they have publicly published hardware description language (HDL) files: gpio ; i2c ; jtag ; pwm ; spi ; timer ; uart ; wdt
( ref: https://www.kernel.org/doc/Documentation/devicetree/bindings/sifive/sifive-blocks-ip-versioning.txt and https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices )

I could be wrong, but that would potentially leave:

  • DMAC x2 (?Direct Memory Access Controller?)
  • Mailbox
  • MIPI-CSI (mobile industry processor interface camera serial interface)
  • ISP-RGB (?Image Signal Processors - Red Green Blue?)
  • 12-bit DVP (?Digital Video Port?)
  • eMMC 5.0 x1
  • Audio DSP (Digital Signal Processing) provided by a HiFi4 (Cadence IP block)
  • I2S/PCM-TDM (Inter-IC Sound bus/Pulse Code Modulation-Time Division Multiplexing)
  • I2S/PCM (Inter-Integrated circuit Sound bus/Pulse Code Modulation)
  • PDM x4 (Pulse-density modulation)
  • SPDIF x1 (Sony/Philips Digital Interface)
  • BootROM (32 KB)
  • DDR external memory I/F LPDDR4/DDR4/DDR3/LPDDR3 32-bit, 2800 Mbps
  • Video Decoder H264/H265 4K @ 60 fps
  • Video Encoder H265 1080p @ 30 fps
  • JPEG Codec
  • HDMI/LCD
  • Display Engine OSD/Overlay
  • MIPI-DSI (mobile industry processor interface display serial interface)
  • PCIe 2.0 1 lane x2* (Peripheral Component Interconnect Express)
  • USB 2.0 Host/Device
  • Ethernet MAC 10/100/1000 Mbps x2
  • CAN 2.0B x2 (Controller Area Network)
  • SDIO 3.0 (Secure Digital Input Output - for MicroSD cards)
  • Power Managment Unit (PMU) CRG (?Clock Reset Generator?)
  • RTC (Real Time Clock)
  • PLL x3 (Phase Locked Loop)
  • OTP (One Time Programmable memory)
  • Secure HW Engine AES/DES/3DES/HASH/PKA

Without any inside knowledge, but having followed news closely, some of these should be commodity. UART is standard 16550, USB should be xHCI, and such.

These parts are probably incompatible in some ways, but remember that these didn’t just fall from the sky. They’re FU740-based designs and that was used in boards like Unmatched long ago. Hundreds of pages of doc is available on those parts. Between JH7100, Unmatched, and other previous generations, we’ve seen open source OSes work through SiFive/StarFive parts before.

Clearly, SiFive has work to do on publishing the official docs that actually match these parts, but they’ve successfully published enough doc on proceeding parts to allow plenty of OSDev work, so I have faith that there won’t be large blocks of parts that’ll create stalls for work.

Looking at public photos of the VisionFive 2 board, I see what might be a VLI VL805-06 chip near the 4 USB 3.0 ports.

VLI VL805 (4-Port Super Speed USB 3.0 Host controller with a PCIe interface)
https://www.via-labs.com/product_show.php?id=48

  • Firmware upgrade options include integrated firmware in system BIOS (I’m guessing would allow OS booting from USB storage devices).

Software:

  • Initial Driver Support for Windows 7, Vista, and XP
  • USB Attached SCSI Protocol (UASP)
  • Supports various Linux kernels
  • Supports Windows 10, Windows 8 inbox driver

Access to the firmware, documentation, and code I would imagine requires signing an NDA, since there is no public datasheet or even brochure, for this VLI confidential information.

There is some public Linux code for the RPi4 which uploads the VL805 firmware blob via a mailbox request to the Videocore OS in the event of a reset, using non public firmware load logic.

So even though basic xHCI functionality can be got to work (if the VL805 loads its own firmware from say an external EEPROM), some possible features may never be added like the ability to boot an OS from a USB storage device, simply because the NDA’s limit access to the knowledge required. And none of information can be made public, so you could end up with a firmware blob that is installed once and never updated.

I should probably add that is not part of the JH7110 SoC.

Actually I’m wrong the VisionFive 2 board has 2x USB 3.0 ports and 2x USB 2.0 ports so maybe the photo I’ve seen is an older revision and the chip used now is not a VL805 4-Port Super Speed USB 3.0 (It might be a VL806 2-Port Super Speed USB 3.0 or possibly a totally different chip which does not need firmware blobs).