New risc-v SBC that looks very interesting indeed. 4x 2ghz cores

Ok, I know this is the competition… etc. But this board really caught my eye earlier in the year but seemed like vapourware at the time.

But Lichee just announced this as shipping later in April’23 and costing $99 plus memory etc.

Lichee Pi 4A
CPU TH1520, 12nm, RISC-V 2.0G C910 x4
Memory 4 / 8 / 16 GB 64bit LPDDR4X-3733
Storage TF Card, or 16 / 32 / 64 / 128 GB eMMC
Network Dual Gigabit Ethernet
USB 4xUSB 3.0 TypeA, 1xUSB2.0 TypeC
Display 1xHDMI2.0 4K@60fps 4-lane MIPI DSI 4K@50fps
Wireless WiFi4+BT5 or WiFi6+BT5
GPIO 2x10 Pin GPIO
Power DC5.5, USB-C, PoE(external)
OS Debian / OpenWRT / Android

The future is looking interesting.


No PCIe.


Yes, there are differences to the JH7110 boards, it will be curious to see how they compare in real-world use.

Video/GPU support looks reasonable, and it has a ‘Speaker Port’ but no fan port. Lol! I actually quite like that.

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I think that we should remember that somewhere I’m sure StarFive are working on the VF3 (or whatever it will be called) and that too will leapfrog the competition. This is a good period for those of us who want to see RISC-V take-up grow to a point where the x86 and ARM curmudgeons STFU… :smiley:

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EDIT: Just to temper your expectations it might take 1.5 to 2 years to get from the start of design to tapeout and about the same to move from initial tapeout to have chips shipping. So from the very start of design to release, would traditionally, be about 3 to 4 years in total. That can be accelerated, by licensing tested and working IP from others.


It’s entirely possible a board based on the 7xxx series could come out before that, just as the JH7110 followed the JH7100.

I suspect there is plenty that could be done with the U7 architecture while the U8 arch is being developed. Especially since the U7 core architecture supports up to 8x cpu’s, and probably better clock speeds too. It will be interesting to look for announcements in the autumn.

Edit: This is what I’m expecting, a 6 or 8 core U7 SOC with other modest incremental improvements, more PCIe lines? 2xGPU’s? SODimm memory?
Releasing a 6 or 8 core design that matches a PI in terms of connectivity would really turn some heads.

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Using swapable/changeable memory modules means changing from LPDDR (Low-Power Double Data Rate) to DDR memory which will use more power. And the shorter signal path length of LPDDR memory means that the clock rate is usually higher, so lower latency, would be increased latency with a lower clock rate using DDR.

The TH1520 itself is a rather interesting chip. It has XuanTie-C910 cores that support vector instructions and can run at 2.5GHz. And there’s a built-in Imagination PowerVR BXM-4-64 video core, and there’s even an Imagination PowerVR AX3386 neural processor. And there’s pretty extensive multimedia codec support. All in all quite an interesting chip which is not inferior in performance to similar arm chips.


however, it’s using rvv 0.71, so current mainline compiler doesn’t support it…


I thought that simply means you don’t get vector accelerated code in the mainline packages, not that it doesn’t work. And recompiling for yourself for this board may be possible (for some). The whole vector instruction ratification thing confuses me, but since it’s not part of the linux risc-v ISA Im not sure it matters much at this stage,

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0.7.1 is incompatible at an assembly language instruction level and a binary level with the ratified vector extension (version 1.0 2021-11). As far as I know most of the people writing compilers have now chosen not to support the non ratified extension, just because they could end up adding support for 100+ minutely different extension.

But you can get a compiler from the chip vendor that has been patched to support 0.7.1. The problem there is that it is then up to the vendor to continuously update their version with any new mainline improvements.

I think that the new “RISC-V Profiles” (see above link) might be very good at pulling things towards a standard.


So if users just stick to the mainstream linux binaries they will be OK, because they are not compiled to use vector instructions at all (ratified or not) since it’s not part of the Linux ISA.

This wont stop people using these boards, it will just mean they feel cheated since it has vector instructions they cannot use, and wont be supported in the future.

If they need one or two application that uses vectors, those binary files could always be statically be compiled with vendors tools. That would be the simplest way.

It is not the end of the world, RISC-V is evolving and fast.

The U74 cores in the JH7110 were almost a RVA20S64_Zba_Zbb under the new RISC-V Profiles (hart naming convention), just missing out because it only supports Ss1p10, and not the now mandatory Ss1p11 (Privileged Architecture version 1.11).

U74 commonly called a “RVI64GC”
(But, the one in the JH7110, is really a rv64imafdcsuxZicsr_Zifencei_Zba_Zbb_Sscofpmf_Sv39_Svbare_Ss1p10_Svade_Ssccptr_Sstvecd_Sstvala)


There is such a thing, but as much as we don’t want the RVV 0.7.1 standard to be with us for a long time. Especially if you take into account the sophgo sg2042, which already uses 64 XuanTie-c920 cores which are also equipped with RVV 0.7.1.


XuanTie-c920 Description.