Milestone Achievement: StarFive's JH7110 Successfully Passes RISC-V Architecture Test

Milestone Achievement: StarFive JH7110 Successfully Passes RISC-V Architecture Test

StarFive is proud to announce the successful upload of the RISC-V Architecture Test report, indicating that the design of JH7110 fully complies with the RVI20 specification requirements. You can find the report at the following link: riscv-non-isa/riscv-arch-test-reports (github.com).

RISC-V Architecture Testing serves as our fundamental screening tool, ensuring that software written for specific RISC-V configurations or specifications can run smoothly on all implementations that comply with those configurations. Additionally, RISC-V Architecture Testing helps ensure that implementers have a correct understanding and implementation of the specification.

Through RISC-V Architecture Testing, we provide users with the assurance that the specification is correctly interpreted, and that the tested implementation (DUT) complies with the guarantees of the RISC-V architecture. Only by passing the architecture test according to the RVI20 standard and obtaining approval from the RISC-V International Organization can the authorization to use the RISC-V trademark be granted in the design.

Following the process illustrated in the above diagram (see 2. Overview — RISCOF 1.23.4 documentation), StarFive has developed a YAML configuration file based on RISCV-CONFIG. This file describes the user’s input of ISA information and validates the legality of the provided register data. Furthermore, we have provided a toolchain for compiling, linking, extracting, and translating target file information for the testing framework. In addition, a Python plugin for JTAG+OpenOCD has been developed specifically for RVI20 testing of JH7110. Through these efforts, JH7110 has successfully passed the ACT testing according to the RVI20 standard.

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The successful completion of the standard testing and recognition by the RISC-V International for JH7110 marks an important milestone in the development of a series of JH7110 solutions that can be regarded as RISC-V ISA compatible. We take great pride in this achievement and remain committed to delivering innovative solutions that comply with the RISC-V standard, providing customers with reliable and efficient products and services.

11 Likes

On Linux for “cat /proc/cpuinfo” in the future can we expect to see RV64IMAFDCZicsr_Zifencei_Zba_Zbb
or
RV64GCZicsr_Zifencei_Zba_Zbb
or (since Zicsr and Zifencei are only accessible in machine mode privilege level)
RV64GCZba_Zbb or RV64IMAFDCZba_Zbb
instead of
rv64imafdc

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Congrats to StarFive!

It is impressive what the VF2 can do already given how new rv64 is. It’ll be even better when Linux kernel support gets mainlined.

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Please accept my sincere congratulations & wishing you as a team more success in the RV field!
Nicely done

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I would like it to be more descriptive than a current one, akin to x86. Like if we copy x86 behavior in some aspects (for example, page size and hugepages), why not align cpuinfo so?

1 Like