What is the Memory Ordering model followed by the StarFive JH7110
I think that should be rvwmo… Please check U74 core manual for more info
I’d expect @Stat_headcrabed 's answer to be true, but would also verify it before relying on it. (Maybe because that’s just the memory model that’s been the norm for decades…ouside of Intel’s TSO magic.)
I think I remember that it can be changed on a per page basis to some - but not all - of of the models by tweaking bits in the PTEs. This was outside the ISA and came in as an errata or supplemental doc or an extension or something between the time RISC-V jumped from QEmu and FPGA onto real silicon where they had real caches and were fast enough to matter. I’m a bit fuzzy on it.
Once you’ve found the answer for sure, please do be sure to post back here, @deependra , for the benefit of others.