Does the JH7110 Support RISC-V Extension D?

Does the JH7110 processor support the RISC-V Extension D: Standard Extension for Double-Precision Floating-Point, Version 2.2

See: RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA | Five EmbedDev

yes, U74(JH7110 CPU core) support RV64GC, the letter G means imafd


And Zba (this one matters) and Zbb, see: page 25 of

B (Zba, Zbb) isn’t part of the RVA20 so you shouldn’t distribute binaries compiled for it (as they wouldn’t work on other RISC-V RV64GC cores), but you might consider using these options for your own software. For GCC, use -march=rv64gc_zba_zbb -mcpu=sifive-u74 -mtune=sifive-u74 in addition to your other favorite optimization flags. For LLVM/Clang, this seems to work: -march=native -mtune=native (I don’t generally use Clang).

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Thank you, tommythorn.

Your PDF links goes to a document entitled “SiFive U74-MC Core Complex Manual 21G1.01.00”. On page 27 [PDF sheet 27]

Section “1.4 S7 RISC-V Monitor Core” states:

The U74-MC Core Complex includes a 64-bit S7 RISC-V

Section “1.5 U7 RISC-V Application Cores” states:

The U74-MC Core Complex includes four 64-bit U7 RISC-V cores, which each have a dual issue,in-order execution pipeline, with a peak execution rate of two instructions per clock cycle. Each U7 core supports machine, supervisor, and user privilege modes, as well as standard Multiply (M), Single-Precision Floating Point (F), Double-Precision Floating Point (D), Atomic (A), Compressed (C), and Bit Manipulation (B) RISC-V extensions (RV64GCB).

Since I do not have my VisionFive 2 at this time (still on order), I just wanted to clarify that the PDF referenced suggests a model “U74-MC Core Complex” which suggests five processors and wonder if this PDF is describing a different version than is built into the VisionFive 2. Does the VisionFive 2 contains the U74-MC Core Complex? With all the appendages to various models, it is difficult to know if “U74” means “U74-MC” and whether “U74-MC” is the same as “U74-MC Core Complex”.



Btw which revision of U74-MC and E24 is used in 7110? Documentation of U74-mc on website is 21G1 version and newest seems to be 21G3 version. This seems to affect some compiler options.

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That was a really interesting question. If you see page 137 of the SiFive U74-MC Core Complex Manual, the mimpid CSR has this information. However looking through the kernel, OpenSBI, and U-boot, surprisingly neither OpenSBI nor the Linux prints this (though they have access to it). U-boot appears to be the only one exposing this via the sbi command, but lo and behold, the U-boot that StarFive ships doesn’t appear to have this enabled.

TL;DR: the easiest way to read mimpid currently appear to be writing a dummy kernel module which prints the result of sbi_get_mimpid(). I didn’t go that far.

UPDATE: it looks like the sources on Debian69 aren’t complete; at least I wasn’t able to build a dummy kernel module:

  make -f /lib/modules/5.15.0-starfive/build/Makefile M=$PWD hello-1.ko

  ERROR: Kernel configuration is invalid.
         include/generated/autoconf.h or include/config/auto.conf are missing.
         Run 'make oldconfig && make prepare' on kernel src to fix it.

make: *** [/lib/modules/5.15.0-starfive/build/Makefile:737: include/config/auto.conf] Error 1

Bare metal programming would be easier…but I don’t have debug probe now

Thanks to Chris, now we know,JH7110 is using 0x0421_0427 “21G1.02.00 / llama.02.00-general”

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