You can check the JH7110 datasheet for more detail:U74 MC
and the U74 document from SiFive as well: https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16acba_fu740-c000-manual-v1p6.pdf
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The “Vision and AI Computing” section in the JH7110 datasheet mentions “VP6”, “DLA”, “NNE50”, and “VAD”. May I know if these correspond to integrated hardware in the chip?
I think these are register names and signal names but they do not necessarily mean the correlation between JH7110 and these codenamed hardware. Currently, StarFive opens the preliminary TRM to collect feedback, you may obtain more information there.
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The following assumes you’re talking about risc-v instruction set extensions.
On JH7110, you have S76 and U74
According to OpenSBI’s reporting, U74 has rv64imafdcbx.
starfive’s uboot and linux dtb announce rv64imafdc for U74 and rv64imac for S76, But I believe the bit-manipulation extension is indeed available on both U74 and S76. However, you’d better have test on specific bit-manipulation instruction to confirm its availability. (gcc 12+ supports the b extension)
If you’re using S76 core (highly unlikely), be ware that the atomic instruction support is incomplete. You can only use AMO, not LR/SC due to lacking of data cache.
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Running Debian Linux, all 4 cores have the same isa display:
user@starfive1:/etc$ cat /proc/cpuinfo
processor : 0
hart : 1
isa : rv64imafdc
mmu : sv39
isa-ext :
uarch : sifive,u74-mc
64-bit
i = integer
m = multiply/divide
a = atomic
f = single floating point
d = double-precision floating point
c = compressed instructions
Is this what you’re looking for? They are elaborated in The RISC-V Reader.
I hope this helps.
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rv64imafdc_zicsr_zba_zbb
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For U74 core, only Zba/Zbb supported, not full bit manuplation extension is supported
thank you very much
I cannot understand it correctly.If they don’t have that, why write them? Not in this chip, at least mark it out to prompt
