Bare metal support

Hi,
I understand that the VF2 uses the U74 cpu from SiFive
But when compiling I get the error
Error: unknown CSR `mtvt’

This register should be present in the cpu, So I am assuming the compiler is not supporting it.

Is there a plan to add this register so that customers can use the “asm volatile(“csrr %0, 0x307” : “=r”(mtvt));”
for work on ecalls and other privileged modes?

Thanks

Yes but inside the JH7110 are four U74 cores from Sifive,
Is there a plan to add the register mtvt to the compiler ?

This is the printout from openocd showing the cores
Info : JTAG tap: e24.cpu tap/device found: 0x07110cfd (mfg: 0x67e (Guangdong StarFive Technology Co), part: 0x7110, ver: 0x0)
Info : JTAG tap: u74.cpu tap/device found: 0x07110cfd (mfg: 0x67e (Guangdong StarFive Technology Co), part: 0x7110, ver: 0x0)

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check this: Building Hello World on Freedem-E-SDK fails with "unknown CSR `mtvt'" - General - SiFive Forums

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I had to lookup what “mtvt” was “Machine Trap Vector Table Base Address”.

My very first step would be to check the version of my assembler (“as --version”) if it was failing to understand what should be a valid instruction. My second step would be to upgrade to the very latest “GNU Binutils” package for the OS I was using. And if that was too old then my next step would be to get the very latest source code for for “as” (the GNU assembler) and compile my own “as” (and I would remove the package before I “make install” the newly compiled source code).

Mtvt seems belong to clic spec which isn’t ratified yet. So sifive uses a pre-standard spec version for it and thus it needs a downstream compiler toolchain for it unless you choose to not use clic.

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https://wiki.riscv.org/display/HOME/Fast+Interrupts+TG

I did a “rgrep mtvt *” on the latest binutils source code and the one and only mention of “mtvt” is totally unrelated to RISC-V, for the PowerPC architecture.

So I would agree, until ratified, it is probably not going to be supported upstream.

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I could be wrong but it looks like “mtvt” 0x307 is not in the current draft of riscv privileged instructions. But “mtvec” (0x305) (Machine Trap-Vector Base-Address Register) which is in the current draft is supported by “as” (the GNU assembler) as a draft instruction. To me it looks like “mtvec” has replaced “mtvt”, so I suspect that it might never be added upstream.

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Thanks for taking the time to look at this.

“mtvt” and “mtvec” are used together.
I found a comment is the trap code
“Exceptions always jump to mtvec.BASE regardless of the vectoring mode”

ecalls and physical memory protection, are a big reason to use these new breed of riscv cores.

I suspect the patch is very small.
Thanks Chris

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Hi, if I understand correctly mtvt is only used when the CLIC is available, which is only available in the E24 core.

As mentioned before the mtvt is probably only going to come to gas and llvm-as releases after it’s ratified, though I’d mention that if you use numeric CSR numbers like:

asm volatile("csrr %0, 0x307" : "=r"(mtvt) : :);

It should already be possible on existing assemblers.

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Hi,
Yes it does compile using SiFive tools.
On SiFive’s website they have a freertos example, where mtvt it is used on the u74 core.

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For those that are interested in baremetal, freertos, or hypervisors.
I have added a github repository which has freertos on 4 cores.
git@github.com:strangerover2002/visionfive2-.git

I used the SiFive tools to build it and openocd for the debugger.

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Is this the SiFive tools that I need: https://github.com/sifive/freedom-studio ?

Hi mzs,
yes those are the more user friendly gui based tools.

They also have Releases · sifive/freedom-tools · GitHub.
These are the cmdline tools,
I downloaded riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-centos6

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I’m curious if we could completely drop clic stuff and move to mainline toolchain… Want to test this but my debug probe isn’t here now…