About RISCV's Performance Counters and QEMU

Hi everybody, I recently started using RISCV architectures, I would need a way to access “hpmcounter[3-31]” registers using QEMU emulator.

The kernel used for simulations is a C program, not a heavy operating system, which is why I would need to access the registers mentioned before via assembly.

Trivially accessing any of those registers always returns zero.

The question is:
Are these registers enabled in QEMU? If not, is it possible to enable them or are they hardwired to zero? How?

Trying to access the registers “cycle”, “instret” and “time” the values come out to be non-zero, which is why I think it is also possible to enable “hpmcounter[3-31]”, but the mode of operation is unknown to me, can anyone help me?

The best place to look for an answer would be where there is the highest concentration of knowledge about the application and that is probably going to be https://www.qemu.org/support/ (instead of here).

If it was me looking for an answer I would search the qemu-riscv mailing list (using a keyword like “hpmcounter”) . The other thing I would do is git clone (or download) the source code for qemu and find out which source code files are used (“rgrep -l -i hpmcounter *”) for the function that I am interested in, and then I would speed read the source code.

And I would probably also end up searching the source code of OpenSBI for any mention of “hpmcounter” and “qemu”.

Ok, thank you for your reply, I already asked on QEMU mailing list, now I will go through QEMU code

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