VisionFive 2 Ecosystem Bi-weekly Updates (7.15-7.31)

StarFive News

  1. Forlinx Embedded announces the JH7110-based high-performance RISC-V SOM FET7110-C.
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  1. The VisionFive 2 Embedded Computer is NOW available in Youyeetoo Taobao Shop.

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Community Collaboration

  1. StarFive invites the senior community developer Qiaochu to demostrate a live show of the mid-high end applications on the IAIC Competition.

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  1. RISC-V is now an official Debian architecture. After Debian approves the official support architecture for RISC-V, there may be many dependencies on Debian open source projects to complete support for RISC-V in a short period of time.


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  2. UEFI Blog released an artical about the RSIC-V UEFI ecosystem status with StarFive’s VisionFive 2 as the example.


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  3. For VisionFive 2, an update of the kernel to Linux 5.15.123 will be applied automatically as part of the DietPi update in DietPi v8.20 release.


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  4. A Transformative RISC-V Architecture Collaboration Through MoU Between USM and StarFive Technology International Sdn Bhd.

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Social Media Updates

  1. YouTuber LivingLinux shared a video on generating fractals on the VisionFive 2 RISC-V SBC with FractalNow and Mandelbulber2.


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  2. Gamers Discussion Hub listed Best RISC-V SBCs in 2023 and VisionFive 2 is on the top of the list.


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  3. Koba wrote a tutorial on booting VisionFive 2 from U-Boot in Janpanese.


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  4. Daniel Maslowski aka CyReVolt has announced that oreboot that has DRAM init for VisionFive 2 has been upstreamed.
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  5. The developer “卿小小” has published an article on testing the CPU and DDR functionality of VisionFive 2.


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The last post shows a CoreMark of 4826.254826 (or 3.22 CoreMark/MHz) for 1 HART of the JH7110:
CoreMark 1.0 : 4826.254826 / GCC12.2.0 -O2 -DPERFORMANCE_RUN=1 -lrt / Heap

I compiled CoreMark about a month ago and got a 24% higher result by tweaking the compiler options to use all the available features of the U74-MC in the JH7110 SoC:
CoreMark 1.0 : 5976.961530 / GCC12.2.0 -O2 -march=rv64imafdc_zicsr_zifencei_zba_zbb -mcpu=sifive-u74 -mtune=sifive-7-series -mabi=lp64d -O3 -DPERFORMANCE_RUN=1 -lrt / Heap

CoreMark of 5977 or 3.985 CoreMark/MHz for 1 HART of the JH7110

user@starfive:~/src/coremark$ sudo cpupower frequency-set -g performance
Setting cpu: 0
Setting cpu: 1
Setting cpu: 2
Setting cpu: 3
user@starfive:~/src/coremark$ cpupower frequency-info
analyzing CPU 0:
  driver: cpufreq-dt
  CPUs which run at the same hardware frequency: 0 1 2 3
  CPUs which need to have their frequency coordinated by software: 0 1 2 3
  maximum transition latency:  Cannot determine or is not supported.
  hardware limits: 313 MHz - 1.50 GHz
  available frequency steps:  313 MHz, 375 MHz, 417 MHz, 500 MHz, 625 MHz, 750 MHz, 1.25 GHz, 1.50 GHz
  available cpufreq governors: conservative ondemand userspace powersave performance schedutil
  current policy: frequency should be within 313 MHz and 1.50 GHz.
                  The governor "performance" may decide which speed to use
                  within this range.
  current CPU frequency: 1.50 GHz (asserted by call to hardware)
user@starfive:~/src/coremark$  make PORT_DIR=linux clean
user@starfive:~/src/coremark$  make PORT_DIR=linux XCFLAGS='-march=rv64imafdc_zicsr_zifencei_zba_zbb -mcpu=sifive-u74 -mtune=sifive-7-series -mabi=lp64d -O3'
user@starfive:~/src/coremark$ ./coremark.exe
2K performance run parameters for coremark.
CoreMark Size    : 666
Total ticks      : 18416
Total time (secs): 18.416000
Iterations/Sec   : 5973.066898
Iterations       : 110000
Compiler version : GCC12.2.0
Compiler flags   : -O2 -march=rv64imafdc_zicsr_zifencei_zba_zbb -mcpu=sifive-u74 -mtune=sifive-7-series -mabi=lp64d -O3 -DPERFORMANCE_RUN=1  -lrt
Memory location  : Please put data memory location here
                        (e.g. code in flash, data on heap etc)
seedcrc          : 0xe9f5
[0]crclist       : 0xe714
[0]crcmatrix     : 0x1fd7
[0]crcstate      : 0x8e3a
[0]crcfinal      : 0x33ff
Correct operation validated. See README.md for run and reporting rules.
CoreMark 1.0 : 5973.066898 / GCC12.2.0 -O2 -march=rv64imafdc_zicsr_zifencei_zba_zbb -mcpu=sifive-u74 -mtune=sifive-7-series -mabi=lp64d -O3 -DPERFORMANCE_RUN=1  -lrt / Heap
user@starfive:~/src/coremark$

Or If I use all four HART’s:

user@starfive:~/src/coremark$ make PORT_DIR=linux clean
user@starfive:~/src/coremark$ make PORT_DIR=linux XCFLAGS='-DMULTITHREAD=4 -DUSE_PTHREAD -march=rv64imafdc_zicsr_zifencei_zba_zbb -mcpu=sifive-u74 -mtune=sifive-7-series -mabi=lp64d -O3'
user@starfive:~/src/coremark$ cat run1.log
2K performance run parameters for coremark.
CoreMark Size    : 666
Total ticks      : 18479
Total time (secs): 18.479000
Iterations/Sec   : 23810.812273
Iterations       : 440000
Compiler version : GCC12.2.0
Compiler flags   : -O2 -DMULTITHREAD=4 -DUSE_PTHREAD -march=rv64imafdc_zicsr_zifencei_zba_zbb -mcpu=sifive-u74 -mtune=sifive-7-series -mabi=lp64d -O3 -DPERFORMANCE_RUN=1  -lrt
Parallel PThreads : 4
Memory location  : Please put data memory location here
                        (e.g. code in flash, data on heap etc)
seedcrc          : 0xe9f5
[0]crclist       : 0xe714
[1]crclist       : 0xe714
[2]crclist       : 0xe714
[3]crclist       : 0xe714
[0]crcmatrix     : 0x1fd7
[1]crcmatrix     : 0x1fd7
[2]crcmatrix     : 0x1fd7
[3]crcmatrix     : 0x1fd7
[0]crcstate      : 0x8e3a
[1]crcstate      : 0x8e3a
[2]crcstate      : 0x8e3a
[3]crcstate      : 0x8e3a
[0]crcfinal      : 0x33ff
[1]crcfinal      : 0x33ff
[2]crcfinal      : 0x33ff
[3]crcfinal      : 0x33ff
Correct operation validated. See README.md for run and reporting rules.
CoreMark 1.0 : 23810.812273 / GCC12.2.0 -O2 -DMULTITHREAD=4 -DUSE_PTHREAD -march=rv64imafdc_zicsr_zifencei_zba_zbb -mcpu=sifive-u74 -mtune=sifive-7-series -mabi=lp64d -O3 -DPERFORMANCE_RUN=1  -lrt / Heap / 4:PThreads

I got a CoreMark score of 23811 or 3.968 CoreMark/MHz using all 4 HART’s.

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Thank you for your feedback :smiling_face_with_three_hearts:

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