Hi all,
Actually I want the IPC(Instruction per Clock Cycle) value for VisionFive2 board, If anyone knows please give the reply.
2 Likes
The U74-MC is SiFive IP, so according to their website it is a “Dual Issue, in-order 8 stage Harvard Pipeline”, so I would guess that the very worst case (bad L1 and L2 cache hits) would be about ~1.6 IPC (Instructions Per Cycle) per core (Technically there are 5 cores in the U74-MC, but only 4 are used under Linux and there is also a currently unused E24 in the VF2 SoC. But the E24 would be Single issue.).
I guess under Linux you could claim a worse case total IPC of 6.4 (4x U74 cores). And if you were bare metal programming using all 6 cores you could probably claim an IPC of 9 with the VF2 hardware. But I am only guessing here. The E24 is asynchronous and has a much lower clock rate so the worse case IPC is probably lower than 9 for the whole JH7110 SoC.
4 Likes
Please refer to chapter 3.3 S7 Execution Pipeline and 4.3 U7 Execution Pipeline of this spec. You most likely don’t care about S7, which is currently unused.
You can also figure out the runtime performance through delta(minstret)/delta(mcycle). mcycle means absolute number of clock cycles and minstret means absolute number of instruction retired.
3 Likes
Hell no! 1.6 IPC is about the BEST CASE for dual-isue code that hasn’t been meticulously hand optimised for the specific µarch. On carefully optimised loops you might get close to 2.0. If you are getting significant branch mispredicts or cache misses then you could get 0.1 or 0.2 IPC or worse.
1 Like