HDMI clock配置

edenzhang · November 15, 2023, 6:15am

有小伙伴知道，HDMI那块的Clock如何配置吗？?有什么文档说明吗？

Chloe · November 15, 2023, 6:17am

你好，看下这个文档有你要的东西吗？

edenzhang · November 15, 2023, 6:25am

感谢提供文档。我想要的是配置clock的过程，先配置哪块，后配置哪块，设置什么寄存器之类的

ganboing · November 15, 2023, 11:31pm

HDMI driver负责通知clock driver和reset driver怎么设置时钟和怎么reset。HDMI driver不关心具体clock/reset的寄存器。

github.com

starfive-tech/linux/blob/VF2_v3.8.2/drivers/gpu/drm/verisilicon/inno_hdmi.c#L966


      
          		return ERR_PTR(ret);
          	}
          
          
	hdmi->i2c = i2c;
          
          
	DRM_DEV_INFO(hdmi->dev, "registered %s I2C bus driver success\n", adap->name);
          
          
	return adap;
          }
          
          
static int inno_hdmi_get_clk_rst(struct device *dev, struct inno_hdmi *hdmi)
          {
          	hdmi->sys_clk = devm_clk_get(dev, "sysclk");
          	if (IS_ERR(hdmi->sys_clk)) {
          		DRM_DEV_ERROR(dev, "Unable to get HDMI sysclk clk\n");
          		return PTR_ERR(hdmi->sys_clk);
          	}
          	hdmi->mclk = devm_clk_get(dev, "mclk");
          	if (IS_ERR(hdmi->mclk)) {
          		DRM_DEV_ERROR(dev, "Unable to get HDMI mclk clk\n");
          		return PTR_ERR(hdmi->mclk);

如果你要看怎么操作clock寄存器，那个在

github.com

starfive-tech/linux/blob/VF2_v3.8.2/drivers/clk/starfive/clk-starfive-jh7110-vout.c#L78


      
          			GATE_FLAG_NORMAL, JH7110_DSI_SYS),
          	JH7110_GMUX(JH7110_U0_CDNS_DSITX_CLK_DPI, "u0_cdns_dsiTx_clk_api",
          			GATE_FLAG_NORMAL, PARENT_NUMS_2,
          			JH7110_DC8200_PIX0,
          			JH7110_HDMITX0_PIXELCLK),
          	JH7110_GATE(JH7110_U0_CDNS_DSITX_CLK_TXESC, "u0_cdns_dsiTx_clk_txesc",
          			GATE_FLAG_NORMAL, JH7110_TX_ESC),
          	//mipitx DPHY
          	JH7110_GATE(JH7110_U0_MIPITX_DPHY_CLK_TXESC, "u0_mipitx_dphy_clk_txesc",
          			GATE_FLAG_NORMAL, JH7110_TX_ESC),
          	//hdmi
          	JH7110_GATE(JH7110_U0_HDMI_TX_CLK_MCLK, "u0_hdmi_tx_clk_mclk",
          			GATE_FLAG_NORMAL, JH7110_HDMITX0_MCLK),
          	JH7110_GATE(JH7110_U0_HDMI_TX_CLK_BCLK, "u0_hdmi_tx_clk_bclk",
          			GATE_FLAG_NORMAL, JH7110_HDMITX0_SCK),
          	JH7110_GATE(JH7110_U0_HDMI_TX_CLK_SYS, "u0_hdmi_tx_clk_sys",
          			GATE_FLAG_NORMAL, JH7110_DISP_APB),
          };
          
          
static struct clk_bulk_data vout_top_clks[] = {
          	{ .id = "vout_src" },

寄存器说明在JH7110 TRM的DOM VOUT CRG那个章节

这两者是通过device tree联系起来的

github.com

starfive-tech/linux/blob/VF2_v3.8.2/arch/riscv/boot/dts/starfive/jh7110.dtsi#L1724


      
          		hdmi: hdmi@29590000 {
          			compatible = "starfive,jh7110-hdmi","inno,hdmi";
          			reg = <0x0 0x29590000 0x0 0x4000>;
          			interrupts = <99>;
          			/*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
          			/*clocks = <&cru  PCLK_HDMI>;*/
          			/*clock-names = "pclk";*/
          			/*pinctrl-names = "default";*/
          			/*pinctrl-0 = <&hdmi_ctl>;*/
          			status = "disabled";
          			clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
          				 <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
          				 <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
          				 <&hdmitx0_pixelclk>;
          			clock-names = "sysclk", "mclk","bclk","pclk";
          			resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
          			reset-names = "hdmi_tx";
          			#sound-dai-cells = <0>;
          		};
          
          
		sound0: snd-card0 {

edenzhang · November 16, 2023, 6:00am

好的，感谢大佬分享。我先看一下这个代码。另外多问一句，Uboot也是一样的原理嘛？

ganboing · November 16, 2023, 6:15am

完全一样的原理，只是driver code会简单一些，毕竟uboot不需要实现复杂的功能。直接看uboot也行