如何设置dc8200_pix0的时钟频率为148.5Mhz？

edenzhang · November 27, 2023, 12:57am

手册上写的是这个寄存器，但它只是个时钟分频器系数

edenzhang · November 27, 2023, 2:33am

It’s been solved

ganboing · November 27, 2023, 2:49am

没错，它是u0_dom_vout_top_clk_dom_vout_top_clk_vout_src 的除频

starfive-tech/linux/blob/VF2_v3.8.2/drivers/clk/starfive/clk-starfive-jh7110-vout.c#L41C56-L41C56


      
          	JH7110__DIV(JH7110_DC8200_PIX0, "dc8200_pix0", 63, JH7110_DISP_ROOT),

github.com

starfive-tech/linux/blob/VF2_v3.8.2/drivers/clk/starfive/clk-starfive-jh7110-vout.c#L231


      
          	pm_runtime_use_autosuspend(&pdev->dev);
          	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
          	pm_runtime_enable(&pdev->dev);
          	ret = pm_runtime_get_sync(&pdev->dev);
          	if (ret < 0) {
          		dev_err(&pdev->dev, "failed to get pm runtime: %d\n", ret);
          		goto init_failed;
          	}
          
          
	//source
          	priv->pll[PLL_OFV(JH7110_DISP_ROOT)] =
          			devm_clk_hw_register_fixed_factor(
          			priv->dev, "disp_root",
          			"u0_dom_vout_top_clk_dom_vout_top_clk_vout_src",
          			0, 1, 1);
          	priv->pll[PLL_OFV(JH7110_DISP_AXI)] =
          			devm_clk_hw_register_fixed_factor(
          			priv->dev, "disp_axi",
          			"u0_dom_vout_top_clk_dom_vout_top_clk_vout_axi",
          			0, 1, 1);
          	priv->pll[PLL_OFV(JH7110_DISP_AHB)] =

u0_dom_vout_top_clk_dom_vout_top_clk_vout_src 只是一个PLL2的gate

github.com

starfive-tech/linux/blob/VF2_v3.8.2/drivers/clk/starfive/clk-starfive-jh7110-sys.c#L152


      
          			CLK_IS_CRITICAL, JH7110_ISP_AXI),
          	//HIFI4
          	JH7110__DIV(JH7110_HIFI4_CORE, "hifi4_core", 15, JH7110_BUS_ROOT),
          	JH7110__DIV(JH7110_HIFI4_AXI, "hifi4_axi", 2, JH7110_HIFI4_CORE),
          	//AXICFG1_DEC
          	JH7110_GATE(JH7110_AXI_CFG1_DEC_CLK_MAIN, "u0_axi_cfg1_dec_clk_main",
          			CLK_IGNORE_UNUSED, JH7110_AXI_CFG1),
          	JH7110_GATE(JH7110_AXI_CFG1_DEC_CLK_AHB, "u0_axi_cfg1_dec_clk_ahb",
          			CLK_IGNORE_UNUSED, JH7110_AHB0),
          	//VOUT
          	JH7110_GATE(JH7110_VOUT_SRC,
          			"u0_dom_vout_top_clk_dom_vout_top_clk_vout_src",
          			GATE_FLAG_NORMAL, JH7110_VOUT_ROOT),
          	JH7110__DIV(JH7110_VOUT_AXI, "vout_axi", 7, JH7110_VOUT_ROOT),
          	JH7110_GATE(JH7110_NOC_BUS_CLK_DISP_AXI,
          			"u0_sft7110_noc_bus_clk_disp_axi",
          			GATE_FLAG_NORMAL, JH7110_VOUT_AXI),
          	JH7110_GATE(JH7110_VOUT_TOP_CLK_VOUT_AHB,
          			"u0_dom_vout_top_clk_dom_vout_top_clk_vout_ahb",
          			GATE_FLAG_NORMAL, JH7110_AHB1),
          	JH7110_GATE(JH7110_VOUT_TOP_CLK_VOUT_AXI,

github.com

starfive-tech/linux/blob/VF2_v3.8.2/drivers/clk/starfive/clk-starfive-jh7110-sys.c#L518


      
          			"u1_reset_ctrl_clk_src", "osc", 0, 1, 1);
          	priv->pll[PLL_OF(JH7110_DDR_ROOT)] =
          			devm_clk_hw_register_fixed_factor(priv->dev,
          			"ddr_root", "pll1_out", 0, 1, 1);
          	priv->pll[PLL_OF(JH7110_VDEC_ROOT)] =
          			devm_clk_hw_register_fixed_factor(priv->dev,
          			"vdec_root", "pll0_out", 0, 1, 1);
          	priv->pll[PLL_OF(JH7110_VENC_ROOT)] =
          			devm_clk_hw_register_fixed_factor(priv->dev,
          			"venc_root", "pll2_out", 0, 1, 1);
          	priv->pll[PLL_OF(JH7110_VOUT_ROOT)] =
          			devm_clk_hw_register_fixed_factor(priv->dev,
          			"vout_root", "pll2_out", 0, 1, 1);
          	priv->pll[PLL_OF(JH7110_GMACUSB_ROOT)] =
          			devm_clk_hw_register_fixed_factor(priv->dev,
          			"gmacusb_root", "pll0_out", 0, 1, 1);
          	priv->pll[PLL_OF(JH7110_PCLK2_MUX_FUNC_PCLK)] =
          			devm_clk_hw_register_fixed_factor(priv->dev,
          			"u2_pclk_mux_func_pclk", "apb_bus_func", 0, 1, 1);
          	priv->pll[PLL_OF(JH7110_PCLK2_MUX_BIST_PCLK)] =
          			devm_clk_hw_register_fixed_factor(priv->dev,

所以PLL2必须设置为1188.0Mhz 的时候才能通过配置/8的方式达到148.5Mhz. 事实上U-boot和Linux都会把PLL2设置为1188.0

edenzhang · November 27, 2023, 7:34am

感谢耐心解答。往offset 0x04写入8即可，目前测试问题已经解决了。