Question about sd-card speed

FWIW, eMMC is a different device from SD. Same peripheral capabilities, but slightly different and unique configuration. Fixes for one may be replicated for the other.

I’m working on fixing SD right now.

SD/EMMC are using the same controller IP and driver, so they share same problems…

It is the same controller IP and driver, but still two separate peripherals and each has different and unique configuration in the device tree. Also, eMMC attributes are not always the same as SD attributes.

Again I am working on fixing SD right now.


@Michael.Zhu Is this a known problem?

I’ve tried setting the UHS flags for sdio1, but it doesn’t appear to be as simple as that. Setting any of them causes the microSD to fail to boot. dtb I generate without the flags boot fine. Don’t have uboot console on the serial port for some reason, so have not looked further. Without a TRM, it’s waiting on the vendor to support higher speeds on the SD interfaces.

For sdcard, on this board it doesn’t support 1.8v io mode for hs200/400 speed mode…
For emmc, some software work need to be done to enable 1.8v supply for it.
(Thanks to neggles from Pine64 community to find out this)

Edit: current discovery is based on v1.2A board schematic, since there are some big changes on v1.3B pcb, we might need to check that version of schematic to confirm if this design problem still exists.


Thank you for this informative reply.

I have Samsung Pro Plus 128gb microsd card (Model MB-MD128KA/KR).
On the x86_64 computer I can get stable speeds about 80-90 Mb/s using Kingston MobileLite G4 (FCR-MLG4) card reader.
But on VF2 the card is detected as SDR50 with 50MHz clock and runs at only ~20 Mb/s (hdparm -t /dev/mmcblk1) - see below:

# dmesg | grep -i mmc
[    0.000000] Kernel command line: root=/dev/mmcblk1p4 rw console=tty0 console=ttyS0,115200 earlycon rootwait stmmaceth=chain_mode:1 selinux=0
[    4.294062] dwmmc_starfive 16010000.sdio0: IDMAC supports 32-bit address mode.
[    4.301403] dwmmc_starfive 16010000.sdio0: Using internal DMA controller.
[    4.309897] dwmmc_starfive 16020000.sdio1: IDMAC supports 32-bit address mode.
[    4.316055] dwmmc_starfive 16010000.sdio0: Version ID is 290a
[    4.316101] dwmmc_starfive 16010000.sdio0: DW MMC controller at irq 29,32 bit host data width,32 deep fifo
[    4.323337] dwmmc_starfive 16020000.sdio1: Using internal DMA controller.
[    4.329187] mmc_host mmc0: card is non-removable.
[    4.338797] dwmmc_starfive 16020000.sdio1: Version ID is 290a
[    4.338847] dwmmc_starfive 16020000.sdio1: DW MMC controller at irq 30,32 bit host data width,32 deep fifo
[    4.350473] mmc_host mmc1: card is polling.
[    4.565739] mmc_host mmc0: Bus speed (slot 0) = 198000000Hz (slot req 400000Hz, actual 399193HZ div = 248)
[    4.575737] mmc_host mmc1: Bus speed (slot 0) = 198000000Hz (slot req 400000Hz, actual 399193HZ div = 248)
[    4.827956] mmc_host mmc1: Bus speed (slot 0) = 198000000Hz (slot req 50000000Hz, actual 49500000HZ div = 2)
[    4.838835] mmc1: new high speed SDXC card at address 59b4
[    4.846238] mmcblk1: mmc1:59b4 FD4Q5 119 GiB 
[    4.861335]  mmcblk1: p1 p2 p3 p4
[    5.015819] mmc_host mmc0: Bus speed (slot 0) = 198000000Hz (slot req 300000Hz, actual 300000HZ div = 330)
[    5.455782] mmc_host mmc0: Bus speed (slot 0) = 198000000Hz (slot req 200000Hz, actual 200000HZ div = 495)
[    5.905840] mmc_host mmc0: Bus speed (slot 0) = 198000000Hz (slot req 100000Hz, actual 100000HZ div = 990)
[    7.671822] EXT4-fs (mmcblk1p4): mounted filesystem with ordered data mode. Opts: (null). Quota mode: disabled.
# hdparm -t /dev/mmcblk1

 Timing buffered disk reads:  66 MB in  3.05 seconds =  21.66 MB/sec

Is it possible to get at least SDR104 mode in U-boot and then in the system on VF2 rev. V1.2a PCB?

1 Like

Edit: after dumping default register config from PMIC under U-Boot, seems eMMC’s power rail already set to 1.8v by default. So the speed issue is becoming more intreresting…

Edit 2: Whatever I change device tree config to, none of them could get a faster read speed than 20M/s… Even kernel reports a MMC clock over 90Mhz

For sd card, it’s power rail is shared between multiple devices due to PMIC on board lacks rails and is set to 3.3V, causing it cannot reach higher speed mode which uses 1.8V mode.
However on-board emmc slot has a dedicated power rail from PMIC, so it’s possible to make it reach maximum speed mode, but current PMIC driver doesn’t support that.
To solve this problem,I’m working on a new driver which could be upstreamed: GitHub - Headcrabed/linux at axp15060
This driver currently lacks GPIO support, and not tested yet. But I’m busy these days to finish this driver…


Edit: Haven’t tested yet, but seems that function implementation is only a simple GPIO edit, might only applicable to their internal EVB. Seems I’m wrong again.

OK, I think I found out the true reason for why eMMC stays at that extremely low speed:
In this commit, they removed dwmci driver’s voltage switch function since SD card doesn’t have a 1.8V power rail as mentioned here. But they forgot that eMMC slot has a proper 1.8V rail. Their upstream version driver also forgot that…
I will test if adding back voltage switch function really helps.


It works!!!

user@starfive:~$ sudo hdparm --direct -t /dev/mmcblk1

 Timing O_DIRECT disk reads: 218 MB in  3.00 seconds =  72.64 MB/sec

Btw seems JH7110’s GPIO cannot handle faster io speed. If I set dts to HS400 mode, speed would be extremely slow.


Nicely done!! I nearly lost the hope that VF2 is faulty.
Which part of it can I take to rebuild? I’m too thirsty for this.

Also it would be cool to share this with U-Boot aswell, as it suffers same problem I think (none of my Uclass microsds which read at least 60~80M/s reach 20M/s in it with mmc read)

This branch is based on sf’s upstream branch (6.3rc+under review patches); only the newest 4 commits are needed (remember there are differences between downstream kernel and this, more commits are needed to port if you want to run it on downstream kernel)


This only works for emmc, SD card doesn’t have 1.8v power rail due to PMIC lacks enough rails for that. 1.8v is a must to reach higher speed.


I’m half wondering if someone at StarFive made a decision for maximum compatibility to (temporarily) limit performance. Get it working now, for as many people as possible, and then tune for performance at some later date.

You mean that microSD’s VDD is 3.3v only right now?

1 Like

If you look at page 2 of the schematic the 3.3V supply (DCDC1) for the SD card is shared with USB 3 (VL805), MIPI LCD, 3.3V supply for the eMMC, MIPI DSI, MIPI CSI and 40 pin GPIO (so it can not be changed to 1.8 volts without disabling a lot of functionality). But the eMMC also has a dedicated connection (ALDO4 AKA VDD_SD AKA VDD1833_SD0 - page 15) from the AXP15060 PMIC (power management integrated circuit), that can have it’s voltage modified (0.7-3.3V @ 300mA).


From what I’m looking at I wonder if some sort of hardware hack is possible. Any ideas?

1 Like

A bodge wire, might be possible in theory, but from where to where is the question (and you will probably end up creating an unshielded loop antenna which will radiate unwanted RF at multiple odd harmonics of the clock frequency). And what functionality would potentially be sacrificed is always the other question. I’ve not checked but I’m guessing that you need 300mA @ 1.8v. So when the MicroSD card is active, what other functionality would never be active that it could share a common voltage supply. Or what function could be fully disabled to supply that 1.8 volts @ 300mA to the MicroSD.

I’m looking at the board and thinking it is way beyond my ability to solder. My first idea would be to de-solder one of the 0.5mm pins (VDD: pin 4 on J10 a TF-15X15) on the MicroSD cardholder slot and bending it away from the PCB pointing to into the air for one end of the bodge (and some Kapton tape underneath the pin to prevent a short, oh and a decoupling capacitor and a bypass capacitor between pin 4 VDD and pin 6 VSS). But then you are faced with the problem where to go next.

It would be high risk.