用Jlink调试S76核心

昉·星光 2(CN)
1

我在尝试将我的rtos移植到jh7110的S76核心上，想用Jlink调试。

根据官方的手册： 使用J-Link连接

我在Ozone中用其中提供的ConnectTAP1脚本成功检测到了U74核心，但是使用ConnectTAP0就失败了，同时J-link进入死机状态需要手动重启

我使用上游u-boot+opensbi，使用u-boot的makefile+opensbi的fw_dynamic.bin构建u-boot镜像烧录，成功进入了uboot。

注意到在spl阶段就已经初始化了jtag端口。

我做的有什么问题吗，有谁有Jlink或者其他调试器连接S76核心的经验吗

2

然后我尝试使用openocd连接，参考官方脚本使用以下脚本

# J-Link setup
adapter speed 10000  ;# kHz

adapter driver jlink
#######################################################
# config core(s)/hart(s) to connect

set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu0 -irlen 5
jtag newtap $_CHIPNAME cpu1 -irlen 5
scan_chain

# -coreid N: hartN, -rtos hwthread: all harts bus only hart0 enabled
# sel_e24: 0 for u7mc, 1 for e2
set sel_e24 1
if { $sel_e24 == 1 } {
	set _TARGETNAME_0 $_CHIPNAME.cpu0

	# e2
	target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu0 -rtos hwthread
	#$_TARGETNAME_0 configure -work-area-phys 0x2a020000 -work-area-size 10000 -work-area-backup 1
} else {
	set _TARGETNAME_0 $_CHIPNAME.cpu0
	set _TARGETNAME_1 $_CHIPNAME.cpu1
	set _TARGETNAME_2 $_CHIPNAME.cpu2
	set _TARGETNAME_3 $_CHIPNAME.cpu3
	set _TARGETNAME_4 $_CHIPNAME.cpu4

	# u7mc
	#target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu1 -rtos hwthread
	target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu1 -coreid 1
	#target create $_TARGETNAME_2 riscv -chain-position $_CHIPNAME.cpu1 -coreid 2
	#target create $_TARGETNAME_3 riscv -chain-position $_CHIPNAME.cpu1 -coreid 3
	#target create $_TARGETNAME_4 riscv -chain-position $_CHIPNAME.cpu1 -coreid 4
	#target smp $_TARGETNAME_0 $_TARGETNAME_1 $_TARGETNAME_2 $_TARGETNAME_3 $_TARGETNAME_4
	#$_TARGETNAME_0 configure -work-area-phys 0x2a020000 -work-area-size 10000 -work-area-backup 1
}

init
halt

if { $sel_e24 == 0 } {
	# e24 is default disabled, shall be enabled from u7mc
	#######enable e24
	##_ENABLE_CLOCK_CLK_U0_E2_SFT7110_CLK_CORE_
	mww phys 0x10230064 0x80000000 ;

	##_ENABLE_CLOCK_CLK_U0_E2_SFT7110_CLK_DBG_
	mww phys 0x10230068 0x80000000 ;

	##_ENABLE_CLOCK_CLK_U0_E2_SFT7110_RTC_CLK_
	mww phys 0x10230060 0x80000018 ;

	##_CLEAR_RESET_RSTGEN_RST_U0_E2_SFT7110_RST_CORE_
	mww phys 0x10230074 0x7fffee ;
}

# zero init L2LIM: secondboot should've done this, if not, read L2LIM will cause exception 1
set zero_L2LIM_len 0
if { $zero_L2LIM_len > 0 } {
	# last 128k is reserved for cache way0
	set L2LIM_size [expr (2 * 1024 - 128) * 1024]
	set L2LIM_start 0x8000000

	if { $zero_L2LIM_len > $L2LIM_size } {
		set zero_L2LIM_len $L2LIM_size
	}
	set end_addr [expr $L2LIM_start + $zero_L2LIM_len]

	set msg [format "zero L2LIM: start 0x%x, size 0x%x" $L2LIM_start $zero_L2LIM_len]
	puts "\n$msg"
	set addr $L2LIM_start
	while { $addr < $end_addr } {
		#set msg [format "wzero %x" $addr]
		#puts "$msg"
		mww phys $addr 0xdeadcafe
		set addr [expr $addr + 4]
	}
	set msg [format "zero L2LIM: size 0x%x done" $zero_L2LIM_len]
	puts "$msg\n"
}

echo "Ready for Remote Connections"

得到结果

Open On-Chip Debugger 0.12.0
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Info : Hardware thread awareness created
Info : J-Link Pro V4 compiled Sep 22 2029 15:00:37
Info : Hardware version: 11.00
Info : VTarget = 3.393 V
Info : clock speed 10000 kHz
Info : JTAG tap: riscv.cpu0 tap/device found: 0x07110cfd (mfg: 0x67e (Guangdong StarFive Technology Co), part: 0x7110, ver: 0x0)
Info : JTAG tap: riscv.cpu1 tap/device found: 0x07110cfd (mfg: 0x67e (Guangdong StarFive Technology Co), part: 0x7110, ver: 0x0)
Info : datacount=1 progbufsize=2
Info : Disabling abstract command reads from CSRs.
Info : Examined RISC-V core; found 1 harts
Info :  hart 0: XLEN=32, misa=0x40901125
Info : starting gdb server for riscv.cpu0 on 3333
Info : Listening on port 3333 for gdb connections
Ready for Remote Connections
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections

tap0上的貌似是e24而非s76核心？其XLEN=32

3

发现官方脚本段中

	target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu1 -rtos hwthread
	target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu1 -coreid 1
	target create $_TARGETNAME_2 riscv -chain-position $_CHIPNAME.cpu1 -coreid 2
	target create $_TARGETNAME_3 riscv -chain-position $_CHIPNAME.cpu1 -coreid 3
    target create $_TARGETNAME_4 riscv -chain-position $_CHIPNAME.cpu1 -coreid 4

猜测：实际上第二个TAP包含S76+U74五个核心
实际运行sel_e24=0的分支，得到结果

Open On-Chip Debugger 0.12.0
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
Info : Hardware thread awareness created
Info : J-Link Pro V4 compiled Sep 22 2029 15:00:37
Info : Hardware version: 11.00
Info : VTarget = 3.393 V
Info : clock speed 10000 kHz
Info : JTAG tap: riscv.cpu0 tap/device found: 0x07110cfd (mfg: 0x67e (Guangdong StarFive Technology Co), part: 0x7110, ver: 0x0)
Info : JTAG tap: riscv.cpu1 tap/device found: 0x07110cfd (mfg: 0x67e (Guangdong StarFive Technology Co), part: 0x7110, ver: 0x0)
Info : datacount=2 progbufsize=16
Info : Disabling abstract command reads from CSRs.
Info : Examined RISC-V core; found 5 harts
Info :  hart 0: XLEN=64, misa=0x8000000000901107
Info : datacount=2 progbufsize=16
Info : Disabling abstract command reads from CSRs.
Info : Examined RISC-V core; found 5 harts
Info :  hart 1: XLEN=64, misa=0x800000000094112f
Info : datacount=2 progbufsize=16
Info : Disabling abstract command reads from CSRs.
Info : Examined RISC-V core; found 5 harts
Info :  hart 2: XLEN=64, misa=0x800000000094112f
Info : datacount=2 progbufsize=16
Info : Disabling abstract command reads from CSRs.
Info : Examined RISC-V core; found 5 harts
Info :  hart 3: XLEN=64, misa=0x800000000094112f
Info : datacount=2 progbufsize=16
Info : Disabling abstract command reads from CSRs.
Info : Examined RISC-V core; found 5 harts
Info :  hart 4: XLEN=64, misa=0x800000000094112f

应该确实如此

4

官方关于J-link连接的描述大概是错误的

5

S76核心是和U74一起的，我没有试过JTAG，但应该是在一个TAP。我倒是试过在S76上跑Linux nommu的同时在U74上跑Linux，是可以做到的。需要注意的是S76没有S模式，也没有MMU。跑任何OS都是做不了内存隔离的。

6

嗯嗯，我明白
实际上，我移植的RTOS之前一直运行在单片机上，也并不依赖MMU

另外，我在尝试用openocd烧录u-boot固件，但貌似openocd并没有jh7110上的qspi驱动？
遇到了一点麻烦

7

个人觉得比较简单的方式是自己做一个占位用的bootloader，它先Init JTAG，然后自旋。这样可以非常方便的直接power on，然后随时接入openocd，直接下载payload，启动。为了防变砖可以先熟悉一下UART boot怎么用。这个“占位”bootloader可以从现有的U-Boot SPL魔改

论调试最方便的还是Hifive Unmatched。它基本上是同样的core complex (U74 x4 + S76)，但是调试方便太多，openocd也有SPI驱动支持。我当时调试vf2是直接刷/插拔了无数遍sdcard